公开(公告)号：US11101268B2

公开(公告)日：2021-08-24

申请号：US16473891

申请日：2017-03-30

Applicant: INTEL CORPORATION

Inventor： Karthik Jambunathan ,  Scott J. Maddox ,  Ritesh Jhaveri ,  Pratik A. Patel ,  Szuya S. Liao ,  Anand S. Murthy ,  Tahir Ghani

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/08 ,  H01L27/088 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/06

Abstract: Techniques are disclosed for forming transistors employing non-selective deposition of source and drain (S/D) material. Non-selectively depositing S/D material provides a multitude of benefits over only selectively depositing the S/D material, such as being able to attain relatively higher dopant activation, steeper dopant profiles, and better channel strain, for example. To achieve selectively retaining non-selectively deposited S/D material only in the S/D regions of a transistor (and not in other locations that would lead to electrically shorting the device, and thus, device failure), the techniques described herein use a combination of dielectric isolation structures, etchable hardmask material, and selective etching processes (based on differential etch rates between monocrystalline semiconductor material, amorphous semiconductor material, and the hardmask material) to selectively remove the non-selectively deposited S/D material and then selectively remove the hardmask material, thereby achieving selective retention of non-selectively deposited monocrystalline semiconductor material in the S/D regions.

公开(公告)号：US11430787B2

公开(公告)日：2022-08-30

申请号：US16639024

申请日：2017-09-26

Applicant: Intel Corporation

Inventor： Karthik Jambunathan ,  Scott J. Maddox ,  Cory C. Bomberger ,  Anand S. Murthy

IPC: H01L27/08 ,  H01L27/088 ,  H01L29/417 ,  H01L29/66 ,  H01L21/285

Abstract: Techniques for forming contacts comprising at least one crystal on source and drain (S/D) regions of semiconductor devices are described. Crystalline S/D contacts can be formed so as to conform to some or all of the top and side surfaces of the S/D regions. Crystalline S/D contacts of the present disclosure are formed by selectively depositing precursor on an exposed portion of one or more S/D regions. The precursor are then reacted in situ on the exposed portion of the S/D region. This reaction forms the conductive, crystalline S/D contact that conforms to the surface of the S/D regions.

公开(公告)号：US20200161440A1

公开(公告)日：2020-05-21

申请号：US16615111

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Ritesh Jhaveri ,  Pratik A. Patel ,  Ralph T. Troeger ,  Szuya S. Liao ,  Karthik Jambunathan ,  Scott J. Maddox ,  Kai Loon Cheong ,  Anand S. Murthy

IPC: H01L29/417 ,  H01L29/08 ,  H01L29/45 ,  H01L29/78 ,  H01L21/285 ,  H01L29/66

Abstract: An apparatus is provided which comprises: a semiconductor region on a substrate, a gate stack on the semiconductor region, a source region comprising doped semiconductor material on the substrate adjacent a first side of the semiconductor region, a drain region comprising doped semiconductor material on the substrate adjacent a second side of the semiconductor region, a substantially conformal semiconductor layer over a surface of a recess in the source region, and a metal over the conformal layer substantially filling the recess in the source region. Other embodiments are also disclosed and claimed.