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    Contact architecture for capacitance reduction and satisfactory contact resistance
    1.
    发明授权
    Contact architecture for capacitance reduction and satisfactory contact resistance 有权

    公开(公告)号：US12224326B2

    公开(公告)日：2025-02-11

    申请号：US18378472

    申请日：2023-10-10

    Applicant: Intel Corporation

    Inventor： Rishabh Mehandru ,  Pratik A. Patel ,  Ralph T. Troeger ,  Szuya S. Liao

    IPC: H01L29/417 ,  H01L21/02 ,  H01L21/265 ,  H01L21/306 ,  H01L21/321 ,  H01L29/08 ,  H01L29/40 ,  H01L29/45 ,  H01L29/49 ,  H01L29/66

    Abstract: Solid assemblies having a composite dielectric spacer and processes for fabricating the solid assemblies are provided. The composite dielectric spacer can include, in some embodiments, a first dielectric layer and a second dielectric layer having a mutual interface. The composite dielectric spacer can separate a contact member from a conductive interconnect member, thus reducing the capacitance between such members with respect to solid assemblies that include one of first dielectric layer or the second dielectric layer. The composite dielectric spacer can permit maintaining the real estate of an interface between the conductive interconnect and a trench contact member that has an interface with a carrier-doped epitaxial layer embodying or constituting a source contact region or a drain contact region of a field effect transistor. The trench contact member can form another interface with the conductive interconnect member, providing a satisfactory contact resistance therebetween.

    Contact architecture for capacitance reduction and satisfactory contact resistance
    3.
    发明授权
    Contact architecture for capacitance reduction and satisfactory contact resistance 有权

    公开(公告)号：US11282930B2

    公开(公告)日：2022-03-22

    申请号：US17085857

    申请日：2020-10-30

    Applicant: Intel Corporation

    Inventor： Rishabh Mehandru ,  Pratik A. Patel ,  Thomas T. Troeger ,  Szuya S. Liao

    IPC: H01L29/417 ,  H01L21/02 ,  H01L21/265 ,  H01L21/306 ,  H01L21/321 ,  H01L29/08 ,  H01L29/40 ,  H01L29/45 ,  H01L29/49 ,  H01L29/66

    Abstract: Solid assemblies having a composite dielectric spacer and processes for fabricating the solid assemblies are provided. The composite dielectric spacer can include, in some embodiments, a first dielectric layer and a second dielectric layer having a mutual interface. The composite dielectric spacer can separate a contact member from a conductive interconnect member, thus reducing the capacitance between such members with respect to solid assemblies that include one of first dielectric layer or the second dielectric layer. The composite dielectric spacer can permit maintaining the real estate of an interface between the conductive interconnect and a trench contact member that has an interface with a carrier-doped epitaxial layer embodying or constituting a source contact region or a drain contact region of a field effect transistor. The trench contact member can form another interface with the conductive interconnect member, providing a satisfactory contact resistance therebetween.

    SELECTIVE DEPOPULATION OF GATE-ALL-AROUND SEMICONDUCTOR DEVICES
    5.
    发明申请
    SELECTIVE DEPOPULATION OF GATE-ALL-AROUND SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20230084182A1

    公开(公告)日：2023-03-16

    申请号：US17473427

    申请日：2021-09-13

    Applicant: Intel Corporation

    Inventor： Mohammad Hasan ,  Tahir Ghani ,  Pratik A. Patel ,  Mohit K. Haran ,  Leonard P. Guler ,  Clifford L. Ong

    IPC: H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L29/786 ,  H01L21/02

    Abstract: Techniques are provided herein to form semiconductor devices having a different number of semiconductor nanoribbons compared to other semiconductor devices on the same substrate. In one example, two different semiconductor devices of a given memory cell, such as a random access memory (RAM) cell, include a p-channel device and an n-channel device. More specifically, the p-channel device may be a GAA transistor with a first number of semiconductor nanoribbons while the n-channel device may be a GAA transistor with a second number of semiconductor nanoribbons that is greater than the first number of semiconductor nanoribbons. In some cases, the n-channel device(s) have one additional semiconductor nanoribbon compared to the p-channel device(s). Depending on when the nanoribbons are removed during the fabrication process, different structural outcomes will occur that can be detected in the final device.

    SELECTIVELY THINNED GATE-ALL-AROUND (GAA) STRUCTURES
    7.
    发明申请
    SELECTIVELY THINNED GATE-ALL-AROUND (GAA) STRUCTURES 有权

    公开(公告)号：US20230079586A1

    公开(公告)日：2023-03-16

    申请号：US17473431

    申请日：2021-09-13

    Applicant: Intel Corporation

    Inventor： Mohammad Hasan ,  Tahir Ghani ,  Pratik A. Patel ,  Leonard P. Guler ,  Mohit K. Haran ,  Clifford L. Ong

    IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/66

    Abstract: Techniques are provided herein to form semiconductor devices having thinned semiconductor regions (e.g., thinner nanoribbons) compared to other semiconductor devices on the same substrate and at a comparable height (e.g., within same layer or adjacent layers). In an example, neighboring semiconductor devices of a given memory cell include a p-channel device and an n-channel device. The p-channel device may be a GAA transistor with a semiconductor nanoribbon having a first width while the n-channel device may be a GAA transistor with a semiconductor nanoribbon having a second width that is larger than the first width (e.g., first width is half the second width). The p-channel device may have a thinner width than the corresponding n-channel device in order to structurally lower the operating current through the p-channel devices by decreasing the width of the active semiconductor channel.

    FIELD EFFECT TRANSISTOR WITH A HYBRID GATE SPACER INCLUDING A LOW-K DIELECTRIC MATERIAL
    8.
    发明申请
    FIELD EFFECT TRANSISTOR WITH A HYBRID GATE SPACER INCLUDING A LOW-K DIELECTRIC MATERIAL 有权

    公开(公告)号：US20220077311A1

    公开(公告)日：2022-03-10

    申请号：US17530741

    申请日：2021-11-19

    Applicant: Intel Corporation

    Inventor： Szuya S. Liao ,  Pratik A. Patel

    IPC: H01L29/78 ,  H01L27/092 ,  H01L29/417 ,  H01L29/66

    Abstract: A FET including a hybrid gate spacer separating a gate electrode from at least one of a source, a drain, or source/drain contact metallization. The hybrid spacer may include a low-k dielectric material for a reduction in parasitic capacitance. The hybrid spacer may further include one or more other dielectric materials of greater relative permittivity that may protect one or more surfaces of the low-k dielectric material from damage by subsequent transistor fabrication operations. The hybrid spacer may include a low-k dielectric material separating a lower portion of a gate electrode sidewall from the source/drain terminal, and a dielectric spacer cap separating to an upper portion of the gate electrode sidewall from the source/drain terminal. The hybrid spacer may have a lower total capacitance than conventional spacers while still remaining robust to downstream fabrication processes. Other embodiments may be described and/or claimed.

    Transistors employing non-selective deposition of source/drain material
    9.
    发明授权
    Transistors employing non-selective deposition of source/drain material 有权

    公开(公告)号：US11101268B2

    公开(公告)日：2021-08-24

    申请号：US16473891

    申请日：2017-03-30

    Applicant: INTEL CORPORATION

    Inventor： Karthik Jambunathan ,  Scott J. Maddox ,  Ritesh Jhaveri ,  Pratik A. Patel ,  Szuya S. Liao ,  Anand S. Murthy ,  Tahir Ghani

    IPC: H01L29/78 ,  H01L29/66 ,  H01L27/08 ,  H01L27/088 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/06

    Abstract: Techniques are disclosed for forming transistors employing non-selective deposition of source and drain (S/D) material. Non-selectively depositing S/D material provides a multitude of benefits over only selectively depositing the S/D material, such as being able to attain relatively higher dopant activation, steeper dopant profiles, and better channel strain, for example. To achieve selectively retaining non-selectively deposited S/D material only in the S/D regions of a transistor (and not in other locations that would lead to electrically shorting the device, and thus, device failure), the techniques described herein use a combination of dielectric isolation structures, etchable hardmask material, and selective etching processes (based on differential etch rates between monocrystalline semiconductor material, amorphous semiconductor material, and the hardmask material) to selectively remove the non-selectively deposited S/D material and then selectively remove the hardmask material, thereby achieving selective retention of non-selectively deposited monocrystalline semiconductor material in the S/D regions.

    Field effect transistor with a hybrid gate spacer including a low-k dielectric material
    10.
    发明授权
    Field effect transistor with a hybrid gate spacer including a low-k dielectric material 有权

    公开(公告)号：US11908940B2

    公开(公告)日：2024-02-20

    申请号：US17530741

    申请日：2021-11-19

    Applicant: Intel Corporation

    Inventor： Szuya S. Liao ,  Pratik A. Patel

    IPC: H01L29/78 ,  H01L27/092 ,  H01L29/417 ,  H01L29/66

    CPC classification number: H01L29/785 ,  H01L27/0924 ,  H01L29/41791 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66795

    Abstract: A FET including a hybrid gate spacer separating a gate electrode from at least one of a source, a drain, or source/drain contact metallization. The hybrid spacer may include a low-k dielectric material for a reduction in parasitic capacitance. The hybrid spacer may further include one or more other dielectric materials of greater relative permittivity that may protect one or more surfaces of the low-k dielectric material from damage by subsequent transistor fabrication operations. The hybrid spacer may include a low-k dielectric material separating a lower portion of a gate electrode sidewall from the source/drain terminal, and a dielectric spacer cap separating to an upper portion of the gate electrode sidewall from the source/drain terminal. The hybrid spacer may have a lower total capacitance than conventional spacers while still remaining robust to downstream fabrication processes. Other embodiments may be described and/or claimed.

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