公开(公告)号：US11824097B2

公开(公告)日：2023-11-21

申请号：US17667493

申请日：2022-02-08

Applicant: Intel Corporation

Inventor： Rishabh Mehandru ,  Pratik A. Patel ,  Ralph T. Troeger ,  Szuya S. Liao

IPC: H01L29/417 ,  H01L21/02 ,  H01L21/265 ,  H01L21/306 ,  H01L21/321 ,  H01L29/08 ,  H01L29/40 ,  H01L29/45 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L29/4175 ,  H01L21/0262 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/26513 ,  H01L21/30604 ,  H01L21/32115 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/45 ,  H01L29/4991 ,  H01L29/665 ,  H01L29/6656

Abstract: Solid assemblies having a composite dielectric spacer and processes for fabricating the solid assemblies are provided. The composite dielectric spacer can include, in some embodiments, a first dielectric layer and a second dielectric layer having a mutual interface. The composite dielectric spacer can separate a contact member from a conductive interconnect member, thus reducing the capacitance between such members with respect to solid assemblies that include one of first dielectric layer or the second dielectric layer. The composite dielectric spacer can permit maintaining the real estate of an interface between the conductive interconnect and a trench contact member that has an interface with a carrier-doped epitaxial layer embodying or constituting a source contact region or a drain contact region of a field effect transistor. The trench contact member can form another interface with the conductive interconnect member, providing a satisfactory contact resistance therebetween.

公开(公告)号：US12224326B2

公开(公告)日：2025-02-11

申请号：US18378472

申请日：2023-10-10

Applicant: Intel Corporation

Inventor： Rishabh Mehandru ,  Pratik A. Patel ,  Ralph T. Troeger ,  Szuya S. Liao

IPC: H01L29/417 ,  H01L21/02 ,  H01L21/265 ,  H01L21/306 ,  H01L21/321 ,  H01L29/08 ,  H01L29/40 ,  H01L29/45 ,  H01L29/49 ,  H01L29/66

Abstract: Solid assemblies having a composite dielectric spacer and processes for fabricating the solid assemblies are provided. The composite dielectric spacer can include, in some embodiments, a first dielectric layer and a second dielectric layer having a mutual interface. The composite dielectric spacer can separate a contact member from a conductive interconnect member, thus reducing the capacitance between such members with respect to solid assemblies that include one of first dielectric layer or the second dielectric layer. The composite dielectric spacer can permit maintaining the real estate of an interface between the conductive interconnect and a trench contact member that has an interface with a carrier-doped epitaxial layer embodying or constituting a source contact region or a drain contact region of a field effect transistor. The trench contact member can form another interface with the conductive interconnect member, providing a satisfactory contact resistance therebetween.

公开(公告)号：US10297499B2

公开(公告)日：2019-05-21

申请号：US15642569

申请日：2017-07-06

Applicant: Intel Corporation

Inventor： Jeffrey S. Leib ,  Ralph T. Troeger ,  Daniel Bergstrom

IPC: H01L29/66 ,  H01L23/528 ,  H01L21/285 ,  H01L21/768 ,  H01L29/417 ,  H01L23/532 ,  H01L23/535 ,  H01L29/78

Abstract: Techniques and methods related to forming a wrap-around contact on a semiconductor device, and apparatus, system, and mobile platform incorporating such semiconductor devices.

公开(公告)号：US20200161440A1

公开(公告)日：2020-05-21

申请号：US16615111

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Ritesh Jhaveri ,  Pratik A. Patel ,  Ralph T. Troeger ,  Szuya S. Liao ,  Karthik Jambunathan ,  Scott J. Maddox ,  Kai Loon Cheong ,  Anand S. Murthy

IPC: H01L29/417 ,  H01L29/08 ,  H01L29/45 ,  H01L29/78 ,  H01L21/285 ,  H01L29/66

Abstract: An apparatus is provided which comprises: a semiconductor region on a substrate, a gate stack on the semiconductor region, a source region comprising doped semiconductor material on the substrate adjacent a first side of the semiconductor region, a drain region comprising doped semiconductor material on the substrate adjacent a second side of the semiconductor region, a substantially conformal semiconductor layer over a surface of a recess in the source region, and a metal over the conformal layer substantially filling the recess in the source region. Other embodiments are also disclosed and claimed.

公开(公告)号：US20170309516A1

公开(公告)日：2017-10-26

申请号：US15642569

申请日：2017-07-06

Applicant: Intel Corporation

Inventor： Jeffrey S. Leib ,  Ralph T. Troeger ,  Daniel Bergstrom

IPC: H01L21/768 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L21/285 ,  H01L23/528 ,  H01L23/532 ,  H01L23/535

CPC classification number: H01L21/76895 ,  H01L21/2855 ,  H01L21/28568 ,  H01L21/76865 ,  H01L21/76883 ,  H01L23/528 ,  H01L23/53266 ,  H01L23/535 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

Abstract: Techniques and methods related to forming a wrap-around contact on a semiconductor device, and apparatus, system, and mobile platform incorporating such semiconductor devices.