公开(公告)号：US11101268B2

公开(公告)日：2021-08-24

申请号：US16473891

申请日：2017-03-30

Applicant: INTEL CORPORATION

Inventor： Karthik Jambunathan ,  Scott J. Maddox ,  Ritesh Jhaveri ,  Pratik A. Patel ,  Szuya S. Liao ,  Anand S. Murthy ,  Tahir Ghani

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/08 ,  H01L27/088 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/06

Abstract: Techniques are disclosed for forming transistors employing non-selective deposition of source and drain (S/D) material. Non-selectively depositing S/D material provides a multitude of benefits over only selectively depositing the S/D material, such as being able to attain relatively higher dopant activation, steeper dopant profiles, and better channel strain, for example. To achieve selectively retaining non-selectively deposited S/D material only in the S/D regions of a transistor (and not in other locations that would lead to electrically shorting the device, and thus, device failure), the techniques described herein use a combination of dielectric isolation structures, etchable hardmask material, and selective etching processes (based on differential etch rates between monocrystalline semiconductor material, amorphous semiconductor material, and the hardmask material) to selectively remove the non-selectively deposited S/D material and then selectively remove the hardmask material, thereby achieving selective retention of non-selectively deposited monocrystalline semiconductor material in the S/D regions.

公开(公告)号：US11011620B2

公开(公告)日：2021-05-18

申请号：US16322815

申请日：2016-09-27

Applicant: INTEL CORPORATION

Inventor： Rishabh Mehandru ,  Cory E. Weber ,  Anand S. Murthy ,  Karthik Jambunathan ,  Glenn A. Glass ,  Jiong Zhang ,  Ritesh Jhaveri ,  Szuya S. Liao

IPC: H01L27/092 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/32

Abstract: Techniques are disclosed for forming increasing channel region tensile strain in n-MOS devices. In some cases, increased channel region tensile strain can be achieved via S/D material engineering that deliberately introduces dislocations in one or both of the S/D regions to produce tensile strain in the adjacent channel region. In some such cases, the S/D material engineering to create desired dislocations may include using a lattice mismatched epitaxial S/D film adjacent to the channel region. Numerous material schemes for achieving multiple dislocations in one or both S/D regions will be apparent in light of this disclosure. In some cases, a cap layer can be formed on an S/D region to reduce contact resistance, such that the cap layer is an intervening layer between the S/D region and S/D contact. The cap layer includes different material than the underlying S/D region and/or a higher dopant concentration to reduce contact resistance.

公开(公告)号：US09923054B2

公开(公告)日：2018-03-20

申请号：US14726282

申请日：2015-05-29

Applicant: Intel Corporation

Inventor： Ritesh Jhaveri ,  Bernard Sell ,  Tahir Ghani

IPC: H01L29/66 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/78

CPC classification number: H01L29/0638 ,  H01L21/823431 ,  H01L21/823821 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/785

Abstract: A hard mask etch stop is formed on the top surface of tall fins to preserve the fin height and protect the top surface of the fin from damage during etching steps of the transistor fabrication process. In an embodiment, the hard mask etch stop is formed using a dual hard mask system, wherein a hard mask etch stop layer is formed over the surface of a substrate, and a second hard mask layer is used to pattern a fin with a hard mask etch stop layer on the top surface of the fin. The second hard mask layer is removed, while the hard mask etch stop layer remains to protect the top surface of the fin during subsequent fabrication steps.

公开(公告)号：US11417531B2

公开(公告)日：2022-08-16

申请号：US17164230

申请日：2021-02-01

Applicant: Intel Corporation

Inventor： Muralidhar S. Ambati ,  Ritesh Jhaveri ,  Moosung Kim

IPC: H01L21/3065 ,  H01L21/308 ,  H01L21/311 ,  H01L29/66 ,  H01L21/324 ,  H01L29/06

Abstract: Embodiments of the invention describe semiconductor devices with high aspect ratio fins and methods for forming such devices. According to an embodiment, the semiconductor device comprises one or more nested fins and one or more isolated fins. According to an embodiment, a patterned hard mask comprising one or more isolated features and one or more nested features is formed with a hard mask etching process. A first substrate etching process forms isolated and nested fins in the substrate by transferring the pattern of the nested and isolated features of the hard mask into the substrate to a first depth. A second etching process is used to etch through the substrate to a second depth. According to embodiments of the invention, the first etching process utilizes an etching chemistry comprising HBr, O2 and CF4, and the second etching process utilizes an etching chemistry comprising Cl2, Ar, and CH4.

公开(公告)号：US10950453B2

公开(公告)日：2021-03-16

申请号：US16836432

申请日：2020-03-31

Applicant: Intel Corporation

Inventor： Muralidhar S. Ambati ,  Ritesh Jhaveri ,  Moosung Kim

IPC: H01L21/3065 ,  H01L21/308 ,  H01L21/311 ,  H01L29/66 ,  H01L21/324 ,  H01L29/06

Abstract: Embodiments of the invention describe semiconductor devices with high aspect ratio fins and methods for forming such devices. According to an embodiment, the semiconductor device comprises one or more nested fins and one or more isolated fins. According to an embodiment, a patterned hard mask comprising one or more isolated features and one or more nested features is formed with a hard mask etching process. A first substrate etching process forms isolated and nested fins in the substrate by transferring the pattern of the nested and isolated features of the hard mask into the substrate to a first depth. A second etching process is used to etch through the substrate to a second depth. According to embodiments of the invention, the first etching process utilizes an etching chemistry comprising HBr, O2 and CF4, and the second etching process utilizes an etching chemistry comprising Cl2, Ar, and CH4.

公开(公告)号：US10147634B2

公开(公告)日：2018-12-04

申请号：US15224987

申请日：2016-08-01

Applicant: INTEL CORPORATION

Inventor： Ritesh Jhaveri ,  Jeanne L. Luce ,  Sang-Won Park ,  Dennis G. Hanken

IPC: H01L21/762 ,  H01L29/06 ,  H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/8234

Abstract: Techniques are disclosed for providing trench isolation of semiconductive fins using flowable dielectric materials. In accordance with some embodiments, a flowable dielectric can be deposited over a fin-patterned semiconductive substrate, for example, using a flowable chemical vapor deposition (FCVD) process. The flowable dielectric may be flowed into the trenches between neighboring fins, where it can be cured in situ, thereby forming a dielectric layer over the substrate, in accordance with some embodiments. Through curing, the flowable dielectric can be converted, for example, to an oxide, a nitride, and/or a carbide, as desired for a given target application or end-use. In some embodiments, the resultant dielectric layer may be substantially defect-free, exhibiting no or an otherwise reduced quantity of seams/voids. After curing, the resultant dielectric layer can undergo wet chemical, thermal, and/or plasma treatment, for instance, to modify at least one of its dielectric properties, density, and/or etch rate.

公开(公告)号：US20150287779A1

公开(公告)日：2015-10-08

申请号：US14726282

申请日：2015-05-29

Applicant: Intel Corporation

Inventor： Ritesh Jhaveri ,  Bernard SELL ,  Tahir GHANI

IPC: H01L29/06 ,  H01L29/78

CPC classification number: H01L29/0638 ,  H01L21/823431 ,  H01L21/823821 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/785

Abstract: A hard mask etch stop is formed on the top surface of tall fins to preserve the fin height and protect the top surface of the fin from damage during etching steps of the transistor fabrication process. In an embodiment, the hard mask etch stop is formed using a dual hard mask system, wherein a hard mask etch stop layer is formed over the surface of a substrate, and a second hard mask layer is used to pattern a fin with a hard mask etch stop layer on the top surface of the fin. The second hard mask layer is removed, while the hard mask etch stop layer remains to protect the top surface of the fin during subsequent fabrication steps.

Abstract translation: 在高鳍的顶表面上形成硬掩模蚀刻停止件以保持翅片高度，并且在晶体管制造工艺的蚀刻步骤期间保护翅片的顶表面免受损坏。 在一个实施例中，使用双硬掩模系统形成硬掩模蚀刻停止件，其中在衬底的表面上形成硬掩模蚀刻停止层，并且使用第二硬掩模层来用硬掩模 在鳍的顶表面上的蚀刻停止层。 去除第二硬掩模层，同时保留硬掩模蚀刻停止层以在随后的制造步骤期间保护翅片的顶表面。

公开(公告)号：US11875999B2

公开(公告)日：2024-01-16

申请号：US17860058

申请日：2022-07-07

Applicant: Intel Corporation

Inventor： Muralidhar S. Ambati ,  Ritesh Jhaveri ,  Moosung Kim

IPC: H01L21/3065 ,  H01L21/308 ,  H01L21/311 ,  H01L29/66 ,  H01L21/324 ,  H01L29/06

CPC classification number: H01L21/3065 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/31116 ,  H01L21/324 ,  H01L29/0642 ,  H01L29/0657 ,  H01L29/66795

Abstract: Embodiments of the invention describe semiconductor devices with high aspect ratio fins and methods for forming such devices. According to an embodiment, the semiconductor device comprises one or more nested fins and one or more isolated fins. According to an embodiment, a patterned hard mask comprising one or more isolated features and one or more nested features is formed with a hard mask etching process. A first substrate etching process forms isolated and nested fins in the substrate by transferring the pattern of the nested and isolated features of the hard mask into the substrate to a first depth. A second etching process is used to etch through the substrate to a second depth. According to embodiments of the invention, the first etching process utilizes an etching chemistry comprising HBr, O2 and CF4, and the second etching process utilizes an etching chemistry comprising Cl2, Ar, and CH4.

公开(公告)号：US11610889B2

公开(公告)日：2023-03-21

申请号：US16145375

申请日：2018-09-28

Applicant: INTEL CORPORATION

Inventor： Anand Murthy ,  Ryan Keech ,  Nicholas G. Minutillo ,  Ritesh Jhaveri

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/51 ,  H01L29/78 ,  H01L29/08 ,  H01L29/49 ,  H01L29/167 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/10

Abstract: Techniques are disclosed for providing an integrated circuit structure having NMOS transistors including an arsenic-doped interface layer between epitaxially grown source/drain regions and a channel region. The arsenic-doped interface layer may include, for example, arsenic-doped silicon (Si:As) having arsenic concentrations in a range of about 1E20 atoms per cm3 to about 5E21 atoms per cm3. The interface layer may have a relatively uniform thickness in a range of about 0.5 nm to full fill where the entire source/drain region is composed of the Si:As. In cases where the arsenic-doped interface layer only partially fills the source/drain regions, another n-type doped semiconductor material can fill remainder (e.g., phosphorus-doped III-V compound or silicon). The use of a layer having a high arsenic concentration can provide improved NMOS performance in the form of abrupt junctions in the source/drain regions and highly conductive source/drain regions with negligible diffusion of arsenic into the channel region.

公开(公告)号：US20200161440A1

公开(公告)日：2020-05-21

申请号：US16615111

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Ritesh Jhaveri ,  Pratik A. Patel ,  Ralph T. Troeger ,  Szuya S. Liao ,  Karthik Jambunathan ,  Scott J. Maddox ,  Kai Loon Cheong ,  Anand S. Murthy

IPC: H01L29/417 ,  H01L29/08 ,  H01L29/45 ,  H01L29/78 ,  H01L21/285 ,  H01L29/66

Abstract: An apparatus is provided which comprises: a semiconductor region on a substrate, a gate stack on the semiconductor region, a source region comprising doped semiconductor material on the substrate adjacent a first side of the semiconductor region, a drain region comprising doped semiconductor material on the substrate adjacent a second side of the semiconductor region, a substantially conformal semiconductor layer over a surface of a recess in the source region, and a metal over the conformal layer substantially filling the recess in the source region. Other embodiments are also disclosed and claimed.