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    Confined epitaxial regions for semiconductor devices
    1.
    发明授权
    Confined epitaxial regions for semiconductor devices 有权

    公开(公告)号：US12094955B2

    公开(公告)日：2024-09-17

    申请号：US18120920

    申请日：2023-03-13

    Applicant: Intel Corporation

    Inventor： Szuya S. Liao ,  Michael L. Hattendorf ,  Tahir Ghani

    IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/165 ,  H01L29/78

    CPC classification number: H01L29/66795 ,  H01L21/823418 ,  H01L21/823431 ,  H01L29/0847 ,  H01L29/6656 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/165

    Abstract: Confined epitaxial regions for semiconductor devices and methods of fabricating semiconductor devices having confined epitaxial regions are described. For example, a semiconductor structure includes a plurality of parallel semiconductor fins disposed above and continuous with a semiconductor substrate. An isolation structure is disposed above the semiconductor substrate and adjacent to lower portions of each of the plurality of parallel semiconductor fins. An upper portion of each of the plurality of parallel semiconductor fins protrudes above an uppermost surface of the isolation structure. Epitaxial source and drain regions are disposed in each of the plurality of parallel semiconductor fins adjacent to a channel region in the upper portion of the semiconductor fin. The epitaxial source and drain regions do not extend laterally over the isolation structure. The semiconductor structure also includes one or more gate electrodes, each gate electrode disposed over the channel region of one or more of the plurality of parallel semiconductor fins.

    Self-aligned gate edge and local interconnect
    2.
    发明授权
    Self-aligned gate edge and local interconnect 有权

    公开(公告)号：US11563081B2

    公开(公告)日：2023-01-24

    申请号：US17000729

    申请日：2020-08-24

    Applicant: Intel Corporation

    Inventor： Milton Clair Webb ,  Mark Bohr ,  Tahir Ghani ,  Szuya S. Liao

    IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/768 ,  H01L21/8238 ,  H01L23/535 ,  H01L27/092 ,  H01L29/417 ,  H01L21/8234

    Abstract: Self-aligned gate edge and local interconnect structures and methods of fabricating self-aligned gate edge and local interconnect structures are described. In an example, a semiconductor structure includes a semiconductor fin disposed above a substrate and having a length in a first direction. A gate structure is disposed over the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate edge isolation structures is centered with the semiconductor fin. A first of the pair of gate edge isolation structures is disposed directly adjacent to the first end of the gate structure, and a second of the pair of gate edge isolation structures is disposed directly adjacent to the second end of the gate structure.

    Contact architecture for capacitance reduction and satisfactory contact resistance
    3.
    发明授权
    Contact architecture for capacitance reduction and satisfactory contact resistance 有权

    公开(公告)号：US11282930B2

    公开(公告)日：2022-03-22

    申请号：US17085857

    申请日：2020-10-30

    Applicant: Intel Corporation

    Inventor： Rishabh Mehandru ,  Pratik A. Patel ,  Thomas T. Troeger ,  Szuya S. Liao

    IPC: H01L29/417 ,  H01L21/02 ,  H01L21/265 ,  H01L21/306 ,  H01L21/321 ,  H01L29/08 ,  H01L29/40 ,  H01L29/45 ,  H01L29/49 ,  H01L29/66

    Abstract: Solid assemblies having a composite dielectric spacer and processes for fabricating the solid assemblies are provided. The composite dielectric spacer can include, in some embodiments, a first dielectric layer and a second dielectric layer having a mutual interface. The composite dielectric spacer can separate a contact member from a conductive interconnect member, thus reducing the capacitance between such members with respect to solid assemblies that include one of first dielectric layer or the second dielectric layer. The composite dielectric spacer can permit maintaining the real estate of an interface between the conductive interconnect and a trench contact member that has an interface with a carrier-doped epitaxial layer embodying or constituting a source contact region or a drain contact region of a field effect transistor. The trench contact member can form another interface with the conductive interconnect member, providing a satisfactory contact resistance therebetween.

    Self-aligned gate edge trigate and finFET devices
    4.
    发明授权
    Self-aligned gate edge trigate and finFET devices 有权

    公开(公告)号：US11043492B2

    公开(公告)日：2021-06-22

    申请号：US16098084

    申请日：2016-07-01

    Applicant: Intel Corporation

    Inventor： Szuya S. Liao ,  Biswajeet Guha ,  Tahir Ghani ,  Christopher N. Kenyon ,  Leonard P. Guler

    IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/66 ,  H01L21/768 ,  H01L23/535

    Abstract: Self-aligned gate edge trigate and finFET devices and methods of fabricating self-aligned gate edge trigate and finFET devices are described. In an example, a semiconductor structure includes a plurality of semiconductor fins disposed above a substrate and protruding through an uppermost surface of a trench isolation region. A gate structure is disposed over the plurality of semiconductor fins. The gate structure defines a channel region in each of the plurality of semiconductor fins. Source and drain regions are on opposing ends of the channel regions of each of the plurality of semiconductor fins, at opposing sides of the gate structure. The semiconductor structure also includes a plurality of gate edge isolation structures. Individual ones of the plurality of gate edge isolation structures alternate with individual ones of the plurality of semiconductor fins.

    Mid-processing removal of semiconductor fins during fabrication of integrated circuit structures
    7.
    发明授权
    Mid-processing removal of semiconductor fins during fabrication of integrated circuit structures 有权

    公开(公告)号：US12266536B2

    公开(公告)日：2025-04-01

    申请号：US18216984

    申请日：2023-06-30

    Applicant: Intel Corporation

    Inventor： Mehmet O. Baykan ,  Anurag Jain ,  Szuya S. Liao

    IPC: H01L21/308 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/10 ,  H01L29/161 ,  H01L29/20

    Abstract: Techniques are disclosed for forming integrated circuit structures having a plurality of semiconductor fins, which in turn can be used to form non-planar transistor structures. The techniques include a mid-process removal of one or more partially-formed fins. The resulting integrated circuit structure includes a plurality of semiconductor fins having relatively uniform dimensions (e.g., fin width and trough depth). In an embodiment, the fin forming procedure includes partially forming a plurality of fins, using a selective etch stop built into the semiconductor structure in which the fins are being formed. One or more of the partially-formed fins are removed via sacrificial fin cut mask layer(s). After fin removal, the process continues by further etching trenches between the partially-formed fins (deep etch) to form portion of fins that will ultimately include transistor channel portion. A liner material may be deposited to protect the partially-formed fins during this subsequent deep trench etch.

    Contact architecture for capacitance reduction and satisfactory contact resistance
    8.
    发明授权
    Contact architecture for capacitance reduction and satisfactory contact resistance 有权

    公开(公告)号：US12224326B2

    公开(公告)日：2025-02-11

    申请号：US18378472

    申请日：2023-10-10

    Applicant: Intel Corporation

    Inventor： Rishabh Mehandru ,  Pratik A. Patel ,  Ralph T. Troeger ,  Szuya S. Liao

    IPC: H01L29/417 ,  H01L21/02 ,  H01L21/265 ,  H01L21/306 ,  H01L21/321 ,  H01L29/08 ,  H01L29/40 ,  H01L29/45 ,  H01L29/49 ,  H01L29/66

    Abstract: Solid assemblies having a composite dielectric spacer and processes for fabricating the solid assemblies are provided. The composite dielectric spacer can include, in some embodiments, a first dielectric layer and a second dielectric layer having a mutual interface. The composite dielectric spacer can separate a contact member from a conductive interconnect member, thus reducing the capacitance between such members with respect to solid assemblies that include one of first dielectric layer or the second dielectric layer. The composite dielectric spacer can permit maintaining the real estate of an interface between the conductive interconnect and a trench contact member that has an interface with a carrier-doped epitaxial layer embodying or constituting a source contact region or a drain contact region of a field effect transistor. The trench contact member can form another interface with the conductive interconnect member, providing a satisfactory contact resistance therebetween.

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