公开(公告)号：US20220367104A1

公开(公告)日：2022-11-17

申请号：US17873518

申请日：2022-07-26

Applicant: Intel Corporation

Inventor： Cheng XU ,  Kyu-Oh LEE ,  Junnan ZHAO ,  Rahul JAIN ,  Ji Yong PARK ,  Sai VADLAMANI ,  Seo Young KIM

IPC: H01F27/28 ,  H01F27/02 ,  H01F27/24

Abstract: Embodiments include an inductor that comprises an inductor trace and a magnetic body surrounding the inductor trace. In an embodiment, the magnetic body comprises a first step surface and a second step surface. Additional embodiments include an inductor that includes a barrier layer. In an embodiment, an inductor trace is formed over a first surface of the barrier layer. Embodiments include a first magnetic body over the inductor trace and the first surface of the barrier layer, and a second magnetic body over a second surface of the barrier layer opposite the first surface. In an embodiment, a width of the second magnetic body is greater than a width of the first magnetic body.

公开(公告)号：US20220328431A1

公开(公告)日：2022-10-13

申请号：US17852003

申请日：2022-06-28

Applicant: Intel Corporation

Inventor： Cheng XU ,  Kyu-Oh LEE ,  Junnan ZHAO ,  Rahul JAIN ,  Ji Yong PARK ,  Sai VADLAMANI ,  Seo Young KIM

IPC: H01L23/64 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48

Abstract: Embodiments include an electronic package that includes a first layer that comprises a dielectric material and a second layer over the first layer, where the second layer comprises a magnetic material. In an embodiment, a third layer is formed over the second layer, where the third layer comprises a dielectric material. In an embodiment, the third layer entirely covers a first surface of the second layer. In an embodiment a first conductive layer and a second conductive layer are embedded within the second layer. In an embodiment, sidewalls of the first conductive layer and the second conductive layer are substantially vertical.

公开(公告)号：US20190206822A1

公开(公告)日：2019-07-04

申请号：US15859481

申请日：2017-12-30

Applicant: Intel Corporation

Inventor： Ji Yong PARK ,  Kyu Oh LEE ,  Cheng XU ,  Seo Young KIM

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L21/4853 ,  H01L23/3157 ,  H01L23/49816 ,  H01L24/11 ,  H01L2224/03019 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05548 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/11019 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/11825 ,  H01L2224/11831 ,  H01L2224/13008 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13082 ,  H01L2224/13147 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/13583 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2224/14131 ,  H01L2224/14133 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/81138 ,  H05K3/4007 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/013

Abstract: Embodiments include semiconductor packages and a method of forming the semiconductor packages. A semiconductor package includes a resist layer disposed on a conductive layer. The semiconductor package also has a bump disposed on the conductive layer. The bump has a top surface and one or more sidewalls. The semiconductor package further includes a surface finish disposed on the top surface and the one or more sidewalls of the bump. The semiconductor package may have the surface finish surround the top surface and sidewalls of the bumps to protect the bumps from Galvanic corrosion. The surface finish may include a nickel-palladium-gold (NiPdAu) surface finish. The semiconductor package may also have a seed disposed on a top surface of the resist layer, and a dielectric disposed on the seed. The dielectric may surround the sidewalls of the bump. The semiconductor package may include the seed to be an electroless copper seed.

公开(公告)号：US20190355675A1

公开(公告)日：2019-11-21

申请号：US15982652

申请日：2018-05-17

Applicant: Intel Corporation

Inventor： Kyu-Oh LEE ,  Sai VADLAMANI ,  Rahul JAIN ,  Junnan ZHAO ,  Ji Yong PARK ,  Cheng XU ,  Seo Young KIM

IPC: H01L23/64 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01F1/12 ,  H01F41/14

Abstract: Techniques for fabricating a semiconductor package having magnetic materials embedded therein are described. For one technique, fabrication of package includes: forming a pad and a conductive line on a build-up layer; forming a raised pad structure on the build-up layer, the raised pad comprising a pillar structure on the pad; encapsulating the conductive line and the raised pad structure in a magnetic film comprising one or more magnetic fillers; planarizing a top surface of the magnetic film until top surfaces of the raised pad structure and the magnetic film are co-planar; depositing a primer layer on the top surfaces; removing one or more portions of the primer layer above the raised pad structure to create an opening; and forming a via in the opening on the raised pad structure. The primer layer may comprise one or more of a build-up layer, a photoimageable dielectric layer, and a metal mask.

公开(公告)号：US20220359115A1

公开(公告)日：2022-11-10

申请号：US17873509

申请日：2022-07-26

Applicant: Intel Corporation

Inventor： Kyu-Oh LEE ,  Rahul JAIN ,  Sai VADLAMANI ,  Cheng XU ,  Ji Yong PARK ,  Junnan ZHAO ,  Seo Young KIM

IPC: H01F27/32 ,  H01L23/498 ,  H01F41/04 ,  H01L21/48 ,  H01F27/28

Abstract: Apparatuses, systems and methods associated with a substrate assembly with an encapsulated magnetic feature for an inductor are disclosed herein. In embodiments, a substrate assembly may include a base substrate, a magnetic feature encapsulated within the base substrate, and a coil, wherein a portion of the coil extends through the magnetic feature. Other embodiments may be described and/or claimed.

公开(公告)号：US20190304933A1

公开(公告)日：2019-10-03

申请号：US15938114

申请日：2018-03-28

Applicant: Intel Corporation

Inventor： Cheng XU ,  Kyu-Oh LEE ,  Junnan ZHAO ,  Rahul JAIN ,  Ji Yong PARK ,  Sai VADLAMANI ,  Seo Young KIM

IPC: H01L23/64 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48

Abstract: Embodiments include an electronic package that includes a first layer that comprises a dielectric material and a second layer over the first layer, where the second layer comprises a magnetic material. In an embodiment, a third layer is formed over the second layer, where the third layer comprises a dielectric material. In an embodiment, the third layer entirely covers a first surface of the second layer. In an embodiment a first conductive layer and a second conductive layer are embedded within the second layer. In an embodiment, sidewalls of the first conductive layer and the second conductive layer are substantially vertical.