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    MAGNETIC BILAYER STRUCTURE FOR A CORED OR CORELESS SEMICONDUCTOR PACKAGE
    1.
    发明申请
    MAGNETIC BILAYER STRUCTURE FOR A CORED OR CORELESS SEMICONDUCTOR PACKAGE 审中-公开

    公开(公告)号：US20190287934A1

    公开(公告)日：2019-09-19

    申请号：US15921511

    申请日：2018-03-14

    Applicant: Intel Corporation

    Inventor： Yikang DENG ,  Jonathan ROSCH ,  Andrew BROWN ,  Junnan ZHAO

    IPC: H01L23/64 ,  H01L23/498 ,  H01L21/48 ,  H01F27/40

    Abstract: Techniques for fabricating a cored or coreless semiconductor package having one or more magnetic bilayer structures embedded therein are described. A magnetic bilayer structure includes a magnetic layer and a dielectric layer. For one technique, fabricating a cored or coreless semiconductor package includes: depositing a seed layer on a build-up layer; forming a raised pad structure and a trace on the seed layer; removing one or more uncovered portions of the seed layer to uncover top surfaces of one or more portions of the build-up layer; applying a magnetic bilayer structure on the raised pad structure, the trace, any unremoved portion of the seed layer, and the top surfaces of the one or more portions of the build-up layer, the magnetic bilayer structure comprises a magnetic layer and a dielectric layer; and forming a conductive structure on the raised pad structure. Other techniques are also described.

    NON-ROUGHENED CU TRACE WITH ANCHORING TO REDUCE INSERTION LOSS OF HIGH SPEED IO ROUTING IN PACKAGE SUBSTRATE
    3.
    发明申请
    NON-ROUGHENED CU TRACE WITH ANCHORING TO REDUCE INSERTION LOSS OF HIGH SPEED IO ROUTING IN PACKAGE SUBSTRATE 审中-公开

    公开(公告)号：US20190295937A1

    公开(公告)日：2019-09-26

    申请号：US15927047

    申请日：2018-03-20

    Applicant: Intel Corporation

    Inventor： Chong ZHANG ,  Ying WANG ,  Cheng XU ,  Hongxia FENG ,  Meizi JIAO ,  Junnan ZHAO ,  Yikang DENG

    IPC: H01L23/498 ,  C23C18/26 ,  H05K1/11 ,  H01L23/00 ,  H01L21/48

    Abstract: Embodiments include semiconductor packages and a method of forming the semiconductor packages. A semiconductor package includes a trace disposed on a conductive layer. The semiconductor package has one or more adhesion anchoring points and a plurality of portions on the trace. An adhesion anchoring point is between two portions on the trace. A surface roughness of an adhesion anchoring point is greater than a surface roughness of a portion on the trace. The trace may be a high-speed input/output (HSIO) trace. The semiconductor package may include via pads disposed on each end of the trace, and a dielectric disposed on the trace. The dielectric is patterned to form openings on the dielectric that expose second portions on the trace. The dielectric remains over the portions. The semiconductor package may have a chemical treatment disposed on the exposed openings on the trace to form the adhesion anchoring points.

    CORE LAYER WITH FULLY ENCAPSULATED CO-AXIAL MAGNETIC MATERIAL AROUND PTH IN IC PACKAGE SUBSTRATE
    9.
    发明申请
    CORE LAYER WITH FULLY ENCAPSULATED CO-AXIAL MAGNETIC MATERIAL AROUND PTH IN IC PACKAGE SUBSTRATE 审中-公开

    公开(公告)号：US20190274217A1

    公开(公告)日：2019-09-05

    申请号：US15910288

    申请日：2018-03-02

    Applicant: Intel Corporation

    Inventor： Chong ZHANG ,  Ying WANG ,  Junnan ZHAO ,  Cheng XU ,  Yikang DENG

    IPC: H05K1/16 ,  H01F27/28 ,  H01L23/498 ,  H01L21/48 ,  H05K1/11 ,  H05K3/00 ,  H05K3/42 ,  H01F41/04

    Abstract: Embodiments may include inductors with embedded magnetic cores and methods of making such inductors. In an embodiment, an integrated circuit package may include an integrated circuit die with a multi-phase voltage regulator electrically coupled to the integrated circuit die. In such embodiments, the multi-phase voltage regulator may include a substrate core and a plurality of inductors. The inductors may include a conductive through-hole disposed through the substrate core and a plugging layer comprising a dielectric material surrounding the conductive through-hole. In an embodiment, a magnetic sheath is formed around the plugging layer. In an embodiment, the magnetic sheath is separated from the plated through hole by the plugging layer. Additionally, a first layer comprising a dielectric material may be disposed over a first surface of the magnetic sheath, and a second layer comprising a dielectric material may be disposed over a second surface of the magnetic sheath.

    FULLY EMBEDDED MAGNETIC-CORE IN CORE LAYER FOR CUSTOM INDUCTOR IN IC SUBSTRATE
    10.
    发明申请
    FULLY EMBEDDED MAGNETIC-CORE IN CORE LAYER FOR CUSTOM INDUCTOR IN IC SUBSTRATE 审中-公开

    公开(公告)号：US20190272936A1

    公开(公告)日：2019-09-05

    申请号：US15911549

    申请日：2018-03-05

    Applicant: Intel Corporation

    Inventor： Chong ZHANG ,  Cheng XU ,  Ying WANG ,  Junnan ZHAO ,  Meizi JIAO ,  Yikang DENG

    IPC: H01F27/24 ,  G05F1/10 ,  H01L49/02 ,  H01F41/02

    Abstract: Embodiments include inductors with embedded magnetic cores and methods of forming such inductors. Some embodiments may include an integrated circuit package that utilizes such inductors. For example, the integrated circuit package may include an integrated circuit die and a multi-phase voltage regulator electrically coupled to the integrated circuit die. In an embodiment, the multi-phase voltage regulator includes a substrate core and a plurality of inductors in the substrate core. In an embodiment, the inductors may include a conductive loop in and around the substrate core. In an embodiment, the conductive loops are electrically coupled to a voltage out line. Embodiments may also include a magnetic core surrounded by the conductive loops. The magnetic core is separated from surfaces of the conductive loops by the substrate core

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