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1.
公开(公告)号:US20240266268A1
公开(公告)日:2024-08-08
申请号:US18612193
申请日:2024-03-21
发明人: SANG-UK KIM
IPC分类号: H01L23/498 , H01L23/00 , H01L23/31 , H01L25/065
CPC分类号: H01L23/49822 , H01L23/3107 , H01L23/49827 , H01L25/0652 , H01L24/05 , H01L24/13 , H01L24/16 , H01L2224/05624 , H01L2224/05647 , H01L2224/05666 , H01L2224/05684 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13118 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/16227 , H01L2924/013
摘要: A semiconductor package includes: a package substrate; a first re-distribution layer disposed on the package substrate; a second re-distribution layer disposed between the package substrate and the first re-distribution layer; a connection substrate interposed between the first re-distribution layer and the second re-distribution layer, wherein a connection hole penetrates the connection substrate; a first semiconductor chip mounted on a first surface of the first re-distribution layer; a first connection chip mounted on a second surface, opposite to the first surface, of the first re-distribution layer and disposed in the connection hole; a second connection chip mounted on a first surface of the second re-distribution layer and disposed in the connection hole; and a first lower semiconductor chip mounted on a second surface, opposite to the first surface, of the second re-distribution layer.
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公开(公告)号:US11756911B2
公开(公告)日:2023-09-12
申请号:US16438578
申请日:2019-06-12
发明人: Krishna Tunga , Ekta Misra
IPC分类号: H01L23/00
CPC分类号: H01L24/13 , H01L24/05 , H01L2224/03462 , H01L2224/03464 , H01L2224/0401 , H01L2224/056 , H01L2224/05012 , H01L2224/05015 , H01L2224/05025 , H01L2224/05027 , H01L2224/0557 , H01L2224/05124 , H01L2224/05144 , H01L2224/05147 , H01L2224/05552 , H01L2224/05555 , H01L2224/05572 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/05686 , H01L2224/10126 , H01L2224/11462 , H01L2224/11464 , H01L2224/13014 , H01L2224/13027 , H01L2224/13082 , H01L2224/13113 , H01L2224/13116 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13166 , H01L2224/13186 , H01L2224/81815 , H01L2924/3512 , H01L2924/35121 , H01L2224/05144 , H01L2924/013 , H01L2924/00014 , H01L2224/05644 , H01L2924/013 , H01L2924/00014 , H01L2224/05647 , H01L2924/013 , H01L2924/00014 , H01L2224/05147 , H01L2924/013 , H01L2924/00014 , H01L2224/05124 , H01L2924/013 , H01L2924/00014 , H01L2224/05624 , H01L2924/013 , H01L2924/00014 , H01L2224/13166 , H01L2924/00014 , H01L2224/05686 , H01L2924/04953 , H01L2924/00014 , H01L2224/13186 , H01L2924/04953 , H01L2924/00014 , H01L2224/13144 , H01L2924/013 , H01L2924/00014 , H01L2224/13147 , H01L2924/013 , H01L2924/00014 , H01L2224/13124 , H01L2924/013 , H01L2924/00014 , H01L2224/13113 , H01L2924/014 , H01L2924/00014 , H01L2224/13139 , H01L2924/014 , H01L2924/00014 , H01L2224/13147 , H01L2924/014 , H01L2924/00014 , H01L2224/13116 , H01L2924/014 , H01L2924/00014 , H01L2224/056 , H01L2924/013 , H01L2924/01013 , H01L2924/01029 , H01L2924/00014 , H01L2224/05647 , H01L2924/013 , H01L2924/01013 , H01L2924/01014 , H01L2924/00014 , H01L2224/05624 , H01L2924/013 , H01L2924/01029 , H01L2924/01014 , H01L2924/00014 , H01L2224/056 , H01L2924/013 , H01L2924/01029 , H01L2924/01013 , H01L2924/00014 , H01L2224/05647 , H01L2924/013 , H01L2924/01014 , H01L2924/01013 , H01L2924/00014
摘要: The present invention provides a structure. In an exemplary embodiment, the structure includes a base material, at least one metal pad, where a first surface of the metal pad is in contact with the base material, and a metal pedestal, where the metal pedestal is in contact with the metal pad, where a radial alignment of the metal pad is shifted by an offset distance, with respect to the metal pedestal, such that the metal pad is shifted towards a center axis of the base material, where a first dimension of the metal pad is smaller than a second dimension of the metal pad, where the second dimension is orthogonal to a line running from a center of the metal pad to the center axis of the base material, where the first dimension is parallel to the line.
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公开(公告)号:US11664335B2
公开(公告)日:2023-05-30
申请号:US15358038
申请日:2016-11-21
IPC分类号: H01L23/00 , H01L23/488
CPC分类号: H01L24/05 , H01L23/488 , H01L24/03 , H01L24/08 , H01L24/48 , H01L24/85 , H01L24/45 , H01L2224/0345 , H01L2224/0347 , H01L2224/03462 , H01L2224/03823 , H01L2224/04042 , H01L2224/05005 , H01L2224/0508 , H01L2224/0516 , H01L2224/05023 , H01L2224/0558 , H01L2224/0566 , H01L2224/05118 , H01L2224/05124 , H01L2224/05139 , H01L2224/05147 , H01L2224/05155 , H01L2224/05164 , H01L2224/05166 , H01L2224/05171 , H01L2224/05172 , H01L2224/05179 , H01L2224/05184 , H01L2224/05186 , H01L2224/05583 , H01L2224/05618 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05664 , H01L2224/05666 , H01L2224/05671 , H01L2224/05672 , H01L2224/05679 , H01L2224/05684 , H01L2224/08503 , H01L2224/45005 , H01L2224/45015 , H01L2224/4554 , H01L2224/45147 , H01L2224/4847 , H01L2224/48247 , H01L2224/48506 , H01L2224/48507 , H01L2224/48855 , H01L2224/85205 , H01L2224/85375 , H01L2924/00014 , H01L2224/45147 , H01L2924/00014 , H01L2224/45015 , H01L2924/2076 , H01L2224/05171 , H01L2924/00014 , H01L2224/05179 , H01L2924/00014 , H01L2224/05172 , H01L2924/00014 , H01L2224/05147 , H01L2924/00014 , H01L2224/05139 , H01L2924/00014 , H01L2224/05164 , H01L2924/00014 , H01L2224/0516 , H01L2924/00014 , H01L2224/05118 , H01L2924/00014 , H01L2224/05155 , H01L2924/00014 , H01L2224/05664 , H01L2924/00014 , H01L2224/05166 , H01L2924/00014 , H01L2224/05184 , H01L2924/00014 , H01L2224/05186 , H01L2924/01074 , H01L2224/05186 , H01L2924/01022 , H01L2224/45005 , H01L2924/2076 , H01L2224/45147 , H01L2924/013 , H01L2924/00014 , H01L2924/00014 , H01L2224/43848 , H01L2224/05644 , H01L2924/00014 , H01L2224/85205 , H01L2924/00014 , H01L2224/05124 , H01L2924/013 , H01L2924/01014
摘要: A power semiconductor chip having: a semiconductor component body; a multilayer metallization arranged on the semiconductor component body; and a nickel layer arranged over the semiconductor component body. The invention further relates to a method for producing a power semiconductor chip and to a power semiconductor device. The invention provides a power semiconductor chip which has a metallization to which a copper wire, provided without a thick metallic coating, can be reliably bonded without damage to the power semiconductor chip during bonding.
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公开(公告)号:US11658172B2
公开(公告)日:2023-05-23
申请号:US16585868
申请日:2019-09-27
发明人: Jing-Cheng Lin
IPC分类号: H01L23/48 , H01L25/00 , H01L21/768 , H01L23/00 , H01L25/065
CPC分类号: H01L25/50 , H01L21/76895 , H01L21/76897 , H01L21/76898 , H01L23/481 , H01L24/05 , H01L24/08 , H01L24/80 , H01L24/89 , H01L25/0657 , H01L2224/0231 , H01L2224/02372 , H01L2224/05024 , H01L2224/0569 , H01L2224/05547 , H01L2224/05576 , H01L2224/05582 , H01L2224/05624 , H01L2224/05647 , H01L2224/08145 , H01L2224/09181 , H01L2224/80075 , H01L2224/80097 , H01L2224/80121 , H01L2224/80204 , H01L2224/80815 , H01L2224/80855 , H01L2224/80895 , H01L2224/80896 , H01L2224/80986 , H01L2224/9202 , H01L2224/94 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2225/06558 , H01L2924/0002 , H01L2924/1304 , H01L2924/0002 , H01L2924/00 , H01L2224/05647 , H01L2924/013 , H01L2924/00014 , H01L2224/05624 , H01L2924/013 , H01L2924/00014 , H01L2224/94 , H01L2224/80001 , H01L2224/80121 , H01L2924/00014 , H01L2224/9202 , H01L2224/11
摘要: A semiconductor device structure is provided. The semiconductor device structure includes a first polymer layer formed between a first substrate and a second substrate, and a first conductive layer formed over the first polymer. The semiconductor device includes a first through substrate via (TSV) formed over the first conductive layer, and the conductive layer is in direct contact with the first TSV and the first polymer.
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公开(公告)号:US20190164782A1
公开(公告)日:2019-05-30
申请号:US15824919
申请日:2017-11-28
发明人: Yu-Lin SHIH , Chih Cheng LEE
IPC分类号: H01L21/48 , H01L23/498 , H01L23/00 , H01L25/065
CPC分类号: H01L21/4857 , H01L21/4853 , H01L23/49811 , H01L23/49822 , H01L23/49838 , H01L24/11 , H01L24/16 , H01L24/17 , H01L24/81 , H01L25/0657 , H01L2224/0401 , H01L2224/1146 , H01L2224/11622 , H01L2224/13147 , H01L2224/16227 , H01L2224/16238 , H01L2224/1703 , H01L2224/81192 , H01L2225/06517 , H01L2225/06548 , H01L2924/15311 , H01L2924/181 , H01L2924/18161 , H01L2924/013 , H01L2924/00014
摘要: A semiconductor substrate includes a dielectric layer, a first patterned conductive layer and a first connection element. The dielectric layer has a first surface. The first patterned conductive layer has a first surface and is disposed adjacent to the first surface of the dielectric layer. The first connection element is disposed on the first surface of the first patterned conductive layer. The first connection element includes a first portion, a second portion and a seed layer disposed between the first portion and the second portion. The first portion of the first connection element and the first patterned conductive layer are formed to be a monolithic structure.
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公开(公告)号:US20190131225A1
公开(公告)日:2019-05-02
申请号:US15976387
申请日:2018-05-10
发明人: Kwang Ok JEONG , Dong Won KANG , Young Gwan KO , Ik Jun CHOI , Jung Soo BYUN
IPC分类号: H01L23/498 , H01L21/48 , H01L25/18 , H01L23/538 , H01L25/00
CPC分类号: H01L23/49822 , H01L21/4853 , H01L21/4857 , H01L23/49894 , H01L23/5383 , H01L24/16 , H01L24/32 , H01L24/73 , H01L24/81 , H01L24/83 , H01L24/92 , H01L25/0655 , H01L25/18 , H01L25/50 , H01L2224/131 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204 , H01L2224/81005 , H01L2224/83005 , H01L2224/92125 , H01L2924/15192 , H01L2924/15313 , H01L2924/18161 , H01L2924/013 , H01L2924/00014
摘要: A semiconductor package includes: a semiconductor chip having an active surface having connection pads disposed thereon; a connection member disposed on the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads; a passivation layer disposed on the connection member; and an underbump metallurgy (UBM) layer embedded in the passivation layer and electrically connected to the redistribution layer of the connection member, wherein the UBM layer includes a UBM pad embedded in the passivation layer, at least one plating layer disposed on the UBM pad and having side surfaces of which at least portions are covered by the UBM pad, and a UBM via penetrating through at least portions of the passivation layer and electrically connecting the redistribution layer of the connection member and the UBM pad to each other.
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公开(公告)号:US20190103391A1
公开(公告)日:2019-04-04
申请号:US16207989
申请日:2018-12-03
发明人: Jui Hsieh Lai , Ying-Hao Kuo , Kuo-Chung Yee
IPC分类号: H01L25/00 , H01L23/48 , H01L23/498 , H01L23/538 , H01L21/48 , H01L23/00 , H01L21/56 , G02B6/42 , G02B6/13 , G02B6/12 , G02B6/132 , G02B6/43
CPC分类号: H01L25/50 , G02B6/12002 , G02B6/13 , G02B6/132 , G02B6/4232 , G02B6/43 , H01L21/481 , H01L21/4853 , H01L21/56 , H01L23/48 , H01L23/49811 , H01L23/5389 , H01L24/13 , H01L24/16 , H01L24/19 , H01L24/20 , H01L24/73 , H01L24/96 , H01L2224/04105 , H01L2224/12105 , H01L2224/13144 , H01L2224/16225 , H01L2224/81192 , H01L2924/00 , H01L2924/0105 , H01L2924/013 , H01L2924/13091
摘要: A semiconductor device includes a first chip, a dielectric layer over the first chip, and a second chip over the dielectric layer. A conductive layer is embedded in the dielectric layer and is electrically coupled to the first chip and the second chip. The second chip includes an optical component. The first chip and the second chip are arranged on opposite sides of the dielectric layer in a thickness direction of the dielectric layer.
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公开(公告)号:US20190103361A1
公开(公告)日:2019-04-04
申请号:US15721788
申请日:2017-09-30
申请人: Intel Corporation
IPC分类号: H01L23/538 , H01L23/12 , H01L23/498 , H01L23/31 , H01L21/56 , H01L23/00
CPC分类号: H01L23/5389 , H01L21/563 , H01L23/12 , H01L23/13 , H01L23/3114 , H01L23/498 , H01L23/5381 , H01L23/5384 , H01L24/13 , H01L24/16 , H01L24/19 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/83 , H01L24/92 , H01L25/0655 , H01L25/50 , H01L2224/131 , H01L2224/16227 , H01L2224/26175 , H01L2224/2919 , H01L2224/32225 , H01L2224/48227 , H01L2224/73204 , H01L2224/83385 , H01L2224/92125 , H01L2924/1432 , H01L2924/1433 , H01L2924/1434 , H01L2924/15311 , H01L2924/013 , H01L2924/00014 , H01L2924/0665
摘要: Electronic device package technology is disclosed. In one example, an electronic device package can include a substrate having a top surface and a vertical surface extending downward from the top surface. The top surface and the vertical surface can define an edge. The electronic device package can also include an electronic component disposed on the top surface of the substrate and electrically coupled to the substrate. In addition, the electronic device package can include an underfill material disposed at least partially between the electronic component and the top surface of the substrate. A lateral portion of the underfill material can extend from the electronic component to at least the edge. Associated systems and methods are also disclosed.
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公开(公告)号:US20190006304A1
公开(公告)日:2019-01-03
申请号:US16010712
申请日:2018-06-18
发明人: Krishna Tunga , Ekta Misra
IPC分类号: H01L23/00
CPC分类号: H01L24/13 , H01L24/05 , H01L2224/03462 , H01L2224/03464 , H01L2224/0401 , H01L2224/05012 , H01L2224/05015 , H01L2224/05025 , H01L2224/05027 , H01L2224/05124 , H01L2224/05144 , H01L2224/05147 , H01L2224/05552 , H01L2224/05555 , H01L2224/0557 , H01L2224/05572 , H01L2224/056 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/05686 , H01L2224/10126 , H01L2224/11462 , H01L2224/11464 , H01L2224/13014 , H01L2224/13027 , H01L2224/13082 , H01L2224/13113 , H01L2224/13116 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13166 , H01L2224/13186 , H01L2224/81815 , H01L2924/3512 , H01L2924/35121 , H01L2924/013 , H01L2924/00014 , H01L2924/04953 , H01L2924/014 , H01L2924/01013 , H01L2924/01029 , H01L2924/01014
摘要: The present invention provides a structure. In an exemplary embodiment, the structure includes a base material, at least one metal pad, where a first surface of the metal pad is in contact with the base material, and a metal pedestal, where the metal pedestal is in contact with the metal pad, where a radial alignment of the metal pad is shifted by an offset distance, with respect to the metal pedestal, such that the metal pad is shifted towards a center axis of the base material, where a first dimension of the metal pad is smaller than a second dimension of the metal pad, where the second dimension is orthogonal to a line running from a center of the metal pad to the center axis of the base material, where the first dimension is parallel to the line.
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10.
公开(公告)号:US20180301395A1
公开(公告)日:2018-10-18
申请号:US16016329
申请日:2018-06-22
发明人: Haruki Ito , Nobuaki Hashimoto
IPC分类号: H01L23/48 , H03H9/10 , H01L23/482 , H03H9/05 , H01L23/50 , H01L23/522 , H01L23/00
CPC分类号: H01L23/481 , H01L23/4824 , H01L23/50 , H01L23/522 , H01L24/12 , H01L2224/05001 , H01L2224/05009 , H01L2224/05022 , H01L2224/05025 , H01L2224/05027 , H01L2224/05124 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05164 , H01L2224/05166 , H01L2224/05171 , H01L2224/05184 , H01L2224/05186 , H01L2224/05548 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/05666 , H01L2224/05671 , H01L2224/05684 , H01L2224/05686 , H01L2224/16 , H01L2924/01019 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/04941 , H01L2924/12042 , H01L2924/14 , H03H9/0547 , H03H9/0552 , H03H9/1071 , H01L2924/00 , H01L2924/00014 , H01L2924/013 , H01L2924/01074 , H01L2924/01023
摘要: A semiconductor device includes an integrated circuit that is disposed at a first face side of a semiconductor substrate, the semiconductor substrate having a first face and a second face, the second face opposing the first face, the semiconductor substrate having a through hole from the first face to the second face; an external connection terminal that is disposed at the first face side; a conductive portion that is disposed in the through hole, the conductive portion being electrically connected to the external connection terminal; and an electronic element that is disposed at a second face side.
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