公开(公告)号：US20240332033A1

公开(公告)日：2024-10-03

申请号：US18614936

申请日：2024-03-25

Applicant: STMicroelectronics International N.V.

Inventor： Michele DERAI ,  Guendalina CATALANO

IPC: H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L21/561 ,  H01L21/78 ,  H01L23/3171 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/94 ,  H01L24/04 ,  H01L2224/0345 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05147 ,  H01L2224/05562 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/11462 ,  H01L2224/11823 ,  H01L2224/11825 ,  H01L2224/13021 ,  H01L2224/13147 ,  H01L2224/13562 ,  H01L2224/13582 ,  H01L2224/13583 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2224/16227 ,  H01L2224/94

Abstract: A “package-less” integrated circuit semiconductor device is produced by laminating first and second insulating films on opposed first and second surfaces of a semiconductor wafer having semiconductor dice integrated therein. Electrically conductive formations towards die pads of the semiconductor dice are provided in vias to the semiconductor wafer opened through the first insulating film laminated on the first surface of the semiconductor wafer. The semiconductor wafer provided with these electrically conductive formations is singulated at separation lines between neighboring semiconductor dice to produce individual semiconductor devices. Each device has: opposed first and second device surfaces having protective portions of the first and second insulating films laminated thereon, and side surfaces extending between the opposed first and second device surfaces, these side surfaces being left uncovered by the first and second insulating films.

公开(公告)号：US20240162163A1

公开(公告)日：2024-05-16

申请号：US18461478

申请日：2023-09-05

Applicant: Texas Instruments Incorporated

Inventor： Sreenivasan K Koduri

IPC: H01L23/552 ,  H01L23/00 ,  H01L23/488

CPC classification number: H01L23/552 ,  H01L23/488 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/95 ,  H01L2224/03318 ,  H01L2224/0401 ,  H01L2224/05006 ,  H01L2224/05007 ,  H01L2224/05025 ,  H01L2224/0508 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05186 ,  H01L2224/05558 ,  H01L2224/05562 ,  H01L2224/05568 ,  H01L2224/05655 ,  H01L2224/11312 ,  H01L2224/1146 ,  H01L2224/11472 ,  H01L2224/1191 ,  H01L2224/13012 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/13618 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/13664 ,  H01L2224/13666 ,  H01L2224/13669 ,  H01L2224/1368 ,  H01L2224/13681 ,  H01L2224/13684 ,  H01L2224/1403 ,  H01L2224/16058 ,  H01L2224/16227 ,  H01L2224/17107 ,  H01L2224/32227 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/83193

Abstract: A microelectronic device includes a die with input/output (I/O) terminals, and a dielectric layer on the die. The microelectronic device includes electrically conductive pillars which are electrically coupled to the I/O terminals, and extend through the dielectric layer to an exterior of the microelectronic device. Each pillar includes a column electrically coupled to one of the I/O terminals, and a head contacting the column at an opposite end of the column from the I/O terminal. The head extends laterally past the column in at least one lateral direction. Methods of forming the pillars and the dielectric layer are disclosed.

公开(公告)号：US11887952B2

公开(公告)日：2024-01-30

申请号：US17875312

申请日：2022-07-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shin-Puu Jeng ,  Shuo-Mao Chen ,  Feng-Cheng Hsu

IPC: H01L21/683 ,  H01L23/31 ,  H01L23/48 ,  H01L25/065 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L25/00 ,  H01L25/10 ,  H01L21/56

CPC classification number: H01L24/08 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/481 ,  H01L24/05 ,  H01L24/11 ,  H01L24/14 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L2221/68331 ,  H01L2221/68345 ,  H01L2224/02145 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13101 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13164 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2224/16225 ,  H01L2224/18 ,  H01L2224/24137 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2225/1058 ,  H01L2924/1203 ,  H01L2924/1304 ,  H01L2924/1432 ,  H01L2924/1436 ,  H01L2924/1461 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19011 ,  H01L2924/19105 ,  H01L2924/3511 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00012 ,  H01L2224/13101 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2224/13655 ,  H01L2924/00014 ,  H01L2224/13644 ,  H01L2924/00014 ,  H01L2224/13664 ,  H01L2924/00014 ,  H01L2224/2919 ,  H01L2924/0665 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/1461 ,  H01L2924/00012 ,  H01L2224/73204 ,  H01L2224/32225 ,  H01L2224/16225 ,  H01L2924/00012 ,  H01L2924/15311 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00012 ,  H01L2224/13144 ,  H01L2924/00014 ,  H01L2224/13164 ,  H01L2924/00014 ,  H01L2924/1304 ,  H01L2924/00012 ,  H01L2924/1436 ,  H01L2924/00012 ,  H01L2924/1203 ,  H01L2924/00012

Abstract: A package structure includes a first dielectric layer, a first semiconductor device over the first dielectric layer, a first redistribution line in the first dielectric layer, a second dielectric layer over the first semiconductor device, a second semiconductor device over the second dielectric layer, a second redistribution line in the second dielectric layer, a conductive through-via over the first dielectric layer and electrically connected to the first redistribution line, a conductive ball over the conductive through-via and electrically connected to the second redistribution line, and a molding material. The molding material surrounds the first semiconductor device, the conductive through-via, and the conductive ball, wherein a top of the conductive ball is higher than a top of the molding material.

公开(公告)号：US20240030145A1

公开(公告)日：2024-01-25

申请号：US18109392

申请日：2023-02-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myungsam KANG

IPC: H01L23/538 ,  H10B80/00 ,  H01L23/00 ,  H01L21/48

CPC classification number: H01L23/5385 ,  H10B80/00 ,  H01L23/5386 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L21/4853 ,  H01L24/11 ,  H01L2224/13147 ,  H01L2224/13007 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/13655 ,  H01L2224/13644 ,  H01L2224/16227 ,  H01L2924/1461 ,  H01L2924/1438 ,  H01L2924/14361 ,  H01L2924/1437 ,  H01L2924/1443 ,  H01L2924/14511 ,  H01L2224/11825

Abstract: A semiconductor package includes a connection substrate with a cavity, a first semiconductor chip and a second semiconductor chip on the connection substrate, a third semiconductor chip in the cavity of the connection substrate, the first semiconductor chip and the second semiconductor chip being on the third semiconductor chip and being connected to each other through the third semiconductor chip, and a molding layer that covers the first semiconductor chip, the second semiconductor chip, and the third semiconductor chip, wherein the third semiconductor chip includes first bumps that are exposed through the molding layer and are connected to the first semiconductor chip and the second semiconductor chip.

公开(公告)号：US11735551B2

公开(公告)日：2023-08-22

申请号：US16363996

申请日：2019-03-25

Applicant: Intel Corporation

Inventor： Jimin Yao ,  Shawna Liff ,  Xin Yan ,  Numair Ahmed

IPC: H01L23/00

CPC classification number: H01L24/17 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/13014 ,  H01L2224/1319 ,  H01L2224/1357 ,  H01L2224/13147 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/1403 ,  H01L2224/14505 ,  H01L2224/171 ,  H01L2224/812 ,  H01L2224/81139 ,  H01L2224/81815 ,  H01L2924/014

Abstract: Embodiments herein relate to systems, apparatuses, or processes directed to an interconnect joint that includes multiple core balls within a solder compound where the multiple core balls are substantially linearly aligned. The multiple core balls, which may include copper or be a polymer, couple with each other within the solder and form a substantially linear alignment during reflow. In embodiments, four or more core balls may be used to achieve a high aspect ratio interconnect joint with a tight pitch.

公开(公告)号：US20230238345A1

公开(公告)日：2023-07-27

申请号：US17707703

申请日：2022-03-29

Applicant: nD-HI Technologies Lab, Inc.

Inventor： Ho-Ming TONG

IPC: H01L23/00 ,  H01L23/498

CPC classification number: H01L24/16 ,  H01L24/13 ,  H01L24/05 ,  H01L24/14 ,  H01L23/49833 ,  H01L2224/16238 ,  H01L2224/13147 ,  H01L2224/0401 ,  H01L2224/05666 ,  H01L2224/05647 ,  H01L2224/13655 ,  H01L2924/014 ,  H01L2224/14517 ,  H01L25/0655

Abstract: This invention provides a high-yielding and high-density/ultra-fine pitch package for ultra-large-scale ICs and advanced ICs. The package includes a substrate and a semiconductor chip. The substrate has a passivation layer covering a first surface of the substrate, wherein a plurality of holes are formed in the passivation layer, and a plurality of solder balls respectively accommodated in the plurality of holes. The semiconductor chip has a first plurality of pads, wherein a plurality of copper pillar micro-bumps respectively extend from the first plurality of pads, and the plurality of copper pillar micro-bumps are respectively connected to the plurality of solder balls.

公开(公告)号：US11682653B2

公开(公告)日：2023-06-20

申请号：US17180364

申请日：2021-02-19

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chih-Ming Hung ,  Meng-Jen Wang ,  Tsung-Yueh Tsai ,  Jen-Kai Ou

IPC: H01L23/00 ,  H01L23/544 ,  H01L21/56 ,  H01L27/146 ,  H01L23/31 ,  G06K9/00 ,  G06V40/13

CPC classification number: H01L24/96 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/31 ,  H01L23/315 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/544 ,  H01L24/13 ,  H01L27/1469 ,  H01L27/14618 ,  H01L27/14634 ,  H01L27/14636 ,  G06V40/1318 ,  G06V40/1329 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2223/54426 ,  H01L2223/54486 ,  H01L2224/13014 ,  H01L2224/1319 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13583 ,  H01L2224/13611 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/95001 ,  H01L2924/014 ,  H01L2924/15321 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00012

Abstract: A semiconductor device includes: a substrate having a first surface and a second surface opposite to the first surface; an electronic component disposed on the first surface of the substrate; a sensor disposed adjacent to the second surface of the substrate; an electrical contact disposed on the first surface of the substrate; and a package body exposing a portion of the electrical contact.

公开(公告)号：US11676926B2

公开(公告)日：2023-06-13

申请号：US17000966

申请日：2020-08-24

Applicant: Schlumberger Technology Corporation

Inventor： Mark Alex Kostinovsky ,  Steven O. Dunford ,  Lweness Mazari

IPC: H01L23/00

CPC classification number: H01L24/16 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/11 ,  H01L24/13 ,  H01L24/43 ,  H01L24/45 ,  H01L24/48 ,  H01L24/81 ,  H01L24/85 ,  H01L24/89 ,  H01L2224/03019 ,  H01L2224/03464 ,  H01L2224/05147 ,  H01L2224/05655 ,  H01L2224/08225 ,  H01L2224/08502 ,  H01L2224/11019 ,  H01L2224/11464 ,  H01L2224/13147 ,  H01L2224/13655 ,  H01L2224/16225 ,  H01L2224/16502 ,  H01L2224/4312 ,  H01L2224/43125 ,  H01L2224/45147 ,  H01L2224/45655 ,  H01L2224/48225 ,  H01L2224/48506 ,  H01L2224/80355 ,  H01L2224/81355 ,  H01L2224/85355 ,  H01L2924/15747

Abstract: A method for interconnecting two conductors includes creating a first nickel layer on a first conductor of an electrical component, producing a first non-gold protective layer on the first nickel layer, the first non-gold protective layer being configured to prevent the first nickel layer from oxidizing, creating a second nickel layer on a second conductor, producing a second non-gold protective layer on the second nickel layer, the second non-gold protective layer being configured to prevent the second nickel layer from oxidizing, and interconnecting the first and second nickel layers using a solder layer that interfaces with the first and second nickel layers between the first and second conductors.

公开(公告)号：US20190206822A1

公开(公告)日：2019-07-04

申请号：US15859481

申请日：2017-12-30

Applicant: Intel Corporation

Inventor： Ji Yong PARK ,  Kyu Oh LEE ,  Cheng XU ,  Seo Young KIM

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L21/4853 ,  H01L23/3157 ,  H01L23/49816 ,  H01L24/11 ,  H01L2224/03019 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05548 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/11019 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/11825 ,  H01L2224/11831 ,  H01L2224/13008 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13082 ,  H01L2224/13147 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/13583 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2224/14131 ,  H01L2224/14133 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/81138 ,  H05K3/4007 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/013

Abstract: Embodiments include semiconductor packages and a method of forming the semiconductor packages. A semiconductor package includes a resist layer disposed on a conductive layer. The semiconductor package also has a bump disposed on the conductive layer. The bump has a top surface and one or more sidewalls. The semiconductor package further includes a surface finish disposed on the top surface and the one or more sidewalls of the bump. The semiconductor package may have the surface finish surround the top surface and sidewalls of the bumps to protect the bumps from Galvanic corrosion. The surface finish may include a nickel-palladium-gold (NiPdAu) surface finish. The semiconductor package may also have a seed disposed on a top surface of the resist layer, and a dielectric disposed on the seed. The dielectric may surround the sidewalls of the bump. The semiconductor package may include the seed to be an electroless copper seed.

公开(公告)号：US20180268724A1

公开(公告)日：2018-09-20

申请号：US15918872

申请日：2018-03-12

Applicant: PRIMAL SPACE SYSTEMS, INC.

Inventor： Barry L. JENKINS

IPC: G08G5/00 ,  H01L23/00 ,  H01L23/31 ,  G05D1/00 ,  G06T15/40 ,  G06T17/05

CPC classification number: G08G5/0069 ,  G05D1/0022 ,  G06T15/40 ,  G06T17/05 ,  G08G5/0008 ,  G08G5/0013 ,  G08G5/0039 ,  G08G5/0052 ,  G08G5/0056 ,  G08G5/0082 ,  G08G5/0086 ,  G08G5/025 ,  G08G5/045 ,  H01L23/3114 ,  H01L23/3157 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0347 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05186 ,  H01L2224/05569 ,  H01L2224/05583 ,  H01L2224/05655 ,  H01L2224/05681 ,  H01L2224/05686 ,  H01L2224/11 ,  H01L2224/11334 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13561 ,  H01L2224/13611 ,  H01L2224/13613 ,  H01L2224/13616 ,  H01L2224/13639 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13681 ,  H01L2224/13686 ,  H01L2924/01046 ,  H01L2924/04941 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/04953 ,  H01L2924/014 ,  H01L2924/01079 ,  H01L2924/01028 ,  H01L2924/01026 ,  H01L2924/01027 ,  H01L2924/01047

Abstract: A method of visibility event navigation includes receiving, via processing circuitry of a client device, a first visibility event packet from a server, the first visibility event packet including information representing 3D surface elements of an environmental model that are occluded from a first viewcell and not occluded from a second viewcell, the first and second viewcells representing spatial regions of a specified navigational route within a real environment modeled by the environmental model. The method also includes acquiring, surface information representing the visible surfaces of the real environment at a sensor and determining, a position in the real environment by matching the surface information to the visibility event packet information. The method further includes transmitting, the position from the client device to the server and receiving a second visibility event packet from the server if the at least one position is within the specified navigational route.