中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

13 records (took 0.04 seconds)

    EDGE COMBINING SUB-HARMONIC N-PATH FILTER
    2.
    发明公开
    EDGE COMBINING SUB-HARMONIC N-PATH FILTER 审中-公开

    公开(公告)号：US20240213947A1

    公开(公告)日：2024-06-27

    申请号：US18088928

    申请日：2022-12-27

    Applicant: Intel Corporation

    Inventor： Run Levinger ,  SOUMYA GUPTA ,  SASHANK KRISHNAMURTHY ,  Ashoke Ravi ,  Ofir Degani

    IPC: H03H7/01

    CPC classification number: H03H7/1758

    Abstract: A filter includes a plurality of filtering paths. The plurality of filtering paths is driven by a corresponding plurality of local oscillator (LO) signals associated with an LO frequency. Each of the LO signals has a phase of a plurality of phases. Each filtering path of the plurality of filtering paths includes a plurality of signal generation branches. The plurality of signal generation branches is configured to receive a harmonic LO signal based on a fraction of the LO frequency, and generate an LO signal of the corresponding plurality of LO signals associated with the LO frequency using the harmonic LO signal.

    QUADRATURE LOCAL OSCILLATOR SIGNAL GENERATION SYSTEMS AND METHODS
    4.
    发明申请
    QUADRATURE LOCAL OSCILLATOR SIGNAL GENERATION SYSTEMS AND METHODS 审中-公开

    公开(公告)号：US20200295765A1

    公开(公告)日：2020-09-17

    申请号：US16352043

    申请日：2019-03-13

    Applicant: Intel Corporation

    Inventor： Abhishek Agrawal ,  Alon Cohen ,  Gil Horovitz ,  Somnath Kundu ,  Run Levinger ,  Stefano Pellerano ,  Jahnavi Sharma ,  Evgeny Shumaker ,  Izhak Hod

    IPC: H03L7/081 ,  H03L7/083

    Abstract: A quadrature based voltage controlled oscillator (VCO) local oscillator (LO) system is disclosed. The system includes a phase detector, a quadrature phase VCO, a quadrature control path, an in-phase control path, and an in-phase VCO. The phase detector is configured to compare and generate phase error between a reference clock and an in-phase VCO output. The quadrature control path configured to generate a quadrature control voltage based on a quadrature VCO output and the in-phase VCO output. The quadrature phase VCO configured to generate the quadrature VCO output based on the quadrature control voltage and the generated phase error. The in-phase control path configured to generate an in-phase control voltage based on the quadrature VCO output and the in-phase VCO output. The in-phase VCO is configured to generate the in-phase VCO output based on the in-phase control voltage and the generated phase error. An all digital dual mode phase locked/phase tracking loop LO generate system is also disclosed.

    High-resolution and agile frequency measurement
    7.
    发明授权
    High-resolution and agile frequency measurement 有权

    公开(公告)号：US11923859B2

    公开(公告)日：2024-03-05

    申请号：US17033122

    申请日：2020-09-25

    Applicant: Intel Corporation

    Inventor： Evgeny Shumaker ,  Sergey Bershansky ,  Ofir Degani ,  Run Levinger

    IPC: H03L7/085 ,  G04F10/00 ,  H03M1/50

    CPC classification number: H03L7/085 ,  G04F10/005 ,  H03M1/50

    Abstract: An apparatus for generating a frequency estimate of an output signal includes a reference signal generator configured to generate a reference clock signal. The apparatus includes frequency estimation circuitry configured to generate a cycle count based frequency estimation of the output signal based on the reference clock signal and a clock cycle count of the output signal. The frequency estimation circuitry further generates a fractional frequency estimation of the output signal based on the reference clock signal and a plurality of time-to-digital conversion phase samples of the output signal. The frequency estimation circuitry further generates the frequency estimate of the output signal using the cycle count based frequency estimation within a range and a frequency error determined from the fractional frequency estimation. The plurality of time-to-digital conversion phase samples and the cycle count based frequency estimation use a same number of reference clock cycles of the reference clock signal.

    Oscillator frequency range extension using switched inductor
    10.
    发明授权
    Oscillator frequency range extension using switched inductor 有权

    公开(公告)号：US11552594B2

    公开(公告)日：2023-01-10

    申请号：US16957349

    申请日：2018-03-30

    Applicant: Intel Corporation

    Inventor： Svetozar Broussev ,  Igor Gertman ,  Eyal Goldberger ,  Run Levinger ,  Ron Pongratz ,  Anat Rubin

    IPC: H03B5/12 ,  H01F17/00 ,  H01F21/12 ,  H01F27/28

    Abstract: An inductive switch comprises an inductor that has a primary metallic winding having a boundary configured in shape of a figure eight, such as in two loops, and a plurality of secondary metallic windings arranged within the boundary of the primary metallic winding. The inductive switch includes a plurality of switches, each switch arranged in series with a respective one of the plurality of secondary metallic windings. An equal number of the secondary windings is arranged within each loop. A tunable inductor comprises at least one main metallic loop and at least one secondary metallic loop, wherein the at least one secondary metallic loop comprises a switch that is arranged to configure the at least one secondary metallic loop into at least one shorted metallic loop or at least one closed metallic loop. The at least one shorted loop is floating.

Patent Agency Ranking