公开(公告)号：US10859627B2

公开(公告)日：2020-12-08

申请号：US15636762

申请日：2017-06-29

Applicant: Intel Corporation

Inventor： Sreejit Chakravarty ,  Oscar Mendoza ,  Ramasubramanian Rajamani ,  Bryan J. Gran ,  Sorin Iacobovici ,  Neel Shah ,  Michael Neve de Mevergnies ,  John Cruz Mejia ,  Amy L. Santoni

IPC: G01R31/317 ,  H04L12/26 ,  G01R31/26 ,  H04L12/24 ,  G01R31/28

Abstract: A processor, including: a core; system test circuitry, the system test circuitry to be locked during operational processor operation; reset circuitry including a kick-off test (KOT) input, the reset circuitry to detect a reset with the KOT input asserted, and to initiate an in-field system test (IFST) mode; a test interface controller to receive in IFST mode an encrypted test packet having a signature, verify the signature of the test packet, and decrypt the test packet; and IFST control circuitry to cause the system test circuitry to perform an IFST test according to the decrypted test packet and to log or report results.

公开(公告)号：US20190007200A1

公开(公告)日：2019-01-03

申请号：US15638162

申请日：2017-06-29

Applicant: INTEL CORPORATION

Inventor： Neel Shah ,  Kirk S. Yap ,  Amy L. Santoni ,  Michael Neve de Mevergnies ,  Oscar Mendoza ,  Sreejit Chakravarty ,  Ramasubramanian Rajamani ,  Bryan J. Gran ,  Sorin Iacobovici

IPC: H04L9/08 ,  G01R31/317 ,  G01R31/26 ,  H04L9/06

Abstract: A processor, including: a core; system test circuitry, the system test circuitry configured to be locked except during an in-field system test (IFST) mode; IFST control circuitry; and a test interface controller, including: a data interface to receive a test packet; a parser to parse the test packet into a key, a signature, and a stored hash-of-hashes; a decryption circuit to decrypt the signature according to the key and to generate a computed hash-of-hashes; a hash circuit to verify the stored hash-of-hashes against the computed hash-of-hashes; and an IFST interface, wherein the test interface controller is to signal the IFST control circuitry to place the system test circuitry in IFST mode.

公开(公告)号：US20200341921A1

公开(公告)日：2020-10-29

申请号：US15931868

申请日：2020-05-14

Applicant: Intel Corporation

Inventor： Gilbert Neiger ,  Rajesh Sankaran ,  Gideon Gerzon ,  Richard Uhlig ,  Sergiu Ghetie ,  Michael Neve de Mevergnies ,  Adil Karrar

IPC: G06F13/26 ,  G06F13/24 ,  G06F9/30 ,  G06F9/455

Abstract: Embodiments of processors, methods, and systems for virtualizing interrupt prioritization and delivery are disclosed. In one embodiment, a processor includes instruction hardware and execution hardware. The instruction hardware is to receive a plurality of instructions, including a first instruction to transfer the processor from a root mode to a non-root mode for executing guest software in a virtual machine, wherein the processor is to return to the root mode upon the detection of any of a plurality of virtual machine exit events. The execution hardware is to execute the first instruction, execution of the first instruction to include determining a first virtual processor-priority value and storing the first virtual processor-priority value in a virtual copy of a processor-priority field, where the virtual copy of the processor-priority field is a virtual resource corresponding to a physical resource associated with an interrupt controller.

公开(公告)号：US20190007212A1

公开(公告)日：2019-01-03

申请号：US15640439

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Michael Neve de Mevergnies ,  Neel Shah ,  Kumar Dwarakanath ,  Fred Bolay ,  Mukesh Kataria

IPC: H04L9/32 ,  G06F21/33

Abstract: Technologies disclosed herein provide an apparatus comprising a fuse controller coupled to an aggregator. The fuse controller includes a plurality of fuses for storing a unique identifier of a device and a first secured value of a first password associated with the unique identifier. The aggregator is to receive the unique identifier and the first secured value from the fuse controller, send the unique identifier to an unlock host, receive a second password from the unlock host, compute a second secured value of the second password using a security function, and unlock one or more privileged features on the device based on the first secured value corresponding to the second secured value. In a specific embodiment, the first secured value corresponds to the second secured value if the first password is equivalent to the second password.

公开(公告)号：US20180129619A1

公开(公告)日：2018-05-10

申请号：US15865430

申请日：2018-01-09

Applicant: Intel Corporation

Inventor： Gilbert Neiger ,  Rajesh Sankaran ,  Gideon Gerzon ,  Richard Uhlig ,  Sergiu Ghetie ,  Michael Neve de Mevergnies ,  Adil Karrar

IPC: G06F13/26 ,  G06F13/24 ,  G06F9/455 ,  G06F9/30

CPC classification number: G06F13/26 ,  G06F9/30076 ,  G06F9/45541 ,  G06F9/45558 ,  G06F13/24 ,  G06F2009/45579 ,  G06F2213/0058

Abstract: Embodiments of processors, methods, and systems for virtualizing interrupt prioritization and delivery are disclosed. In one embodiment, a processor includes instruction hardware and execution hardware. The instruction hardware is to receive a plurality of instructions, including a first instruction to transfer the processor from a root mode to a non-root mode for executing guest software in a virtual machine, wherein the processor is to return to the root mode upon the detection of any of a plurality of virtual machine exit events. The execution hardware is to execute the first instruction, execution of the first instruction to include determining a first virtual processor-priority value and storing the first virtual processor-priority value in a virtual copy of a processor-priority field, where the virtual copy of the processor-priority field is a virtual resource corresponding to a physical resource associated with an interrupt controller.