公开(公告)号：US11417567B2

公开(公告)日：2022-08-16

申请号：US16347184

申请日：2016-12-23

Applicant: Intel Corporation

Inventor： Florian Gstrein ,  Eungnak Han ,  Rami Hourani ,  Ruth A. Brain ,  Paul A. Nyhus ,  Manish Chandhok ,  Charles H. Wallace ,  Chi-Hwa Tsang

IPC: H01L21/768 ,  H01L21/027 ,  H01L23/522 ,  H01L23/528

Abstract: Conductive cap-based approaches for conductive via fabrication is described. In an example, an integrated circuit structure includes a plurality of conductive lines in an ILD layer above a substrate. Each of the conductive lines is recessed relative to an uppermost surface of the ILD layer. A plurality of conductive caps is on corresponding ones of the plurality of conductive lines, in recess regions above each of the plurality of conductive lines. A hardmask layer is on the plurality of conductive caps and on the uppermost surface of the ILD layer. The hardmask layer includes a first hardmask component on and aligned with the plurality of conductive caps, and a second hardmask component on an aligned with regions of the uppermost surface of the ILD layer. A conductive via is in an opening in the hardmask layer and on a conductive cap of one of the plurality of conductive lines.

公开(公告)号：US11869894B2

公开(公告)日：2024-01-09

申请号：US17864264

申请日：2022-07-13

Applicant: Intel Corporation

Inventor： Aaron D. Lilak ,  Anh Phan ,  Patrick Morrow ,  Willy Rachmady ,  Gilbert Dewey ,  Jessica M. Torres ,  Kimin Jun ,  Tristan A. Tronic ,  Christopher J. Jezewski ,  Hui Jae Yoo ,  Robert S. Chau ,  Chi-Hwa Tsang

IPC: H01L27/12 ,  H01L21/02 ,  H01L21/285 ,  H01L21/84 ,  H01L29/08 ,  H01L29/16 ,  H01L29/417 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78 ,  H10B61/00 ,  H10B63/00

CPC classification number: H01L27/1207 ,  H01L21/02532 ,  H01L21/28568 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/66795 ,  H01L29/785 ,  H10B61/22 ,  H10B63/30

Abstract: A stacked device structure includes a first device structure including a first body that includes a semiconductor material, and a plurality of terminals coupled with the first body. The stacked device structure further includes an insulator between the first device structure and a second device structure. The second device structure includes a second body such as a fin structure directly above the insulator. The second device structure further includes a gate coupled to the fin structure, a spacer including a dielectric material adjacent to the gate, and an epitaxial structure adjacent to a sidewall of the fin structure and between the spacer and the insulator. A metallization structure is coupled to a sidewall surface of the epitaxial structure, and further coupled with one of the terminals of the first device.

公开(公告)号：US20220344376A1

公开(公告)日：2022-10-27

申请号：US17864264

申请日：2022-07-13

Applicant: Intel Corporation

Inventor： Aaron D. Lilak ,  Anh Phan ,  Patrick Morrow ,  Willy Rachmady ,  Gilbert Dewey ,  Jessica M. Torres ,  Kimin Jun ,  Tristan A. Tronic ,  Christopher J. Jezewski ,  Hui Jae Yoo ,  Robert S. Chau ,  Chi-Hwa Tsang

IPC: H01L27/12 ,  H01L21/02 ,  H01L21/285 ,  H01L21/84 ,  H01L27/22 ,  H01L27/24 ,  H01L29/08 ,  H01L29/16 ,  H01L29/417 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78

Abstract: A stacked device structure includes a first device structure including a first body that includes a semiconductor material, and a plurality of terminals coupled with the first body. The stacked device structure further includes an insulator between the first device structure and a second device structure. The second device structure includes a second body such as a fin structure directly above the insulator. The second device structure further includes a gate coupled to the fin structure, a spacer including a dielectric material adjacent to the gate, and an epitaxial structure adjacent to a sidewall of the fin structure and between the spacer and the insulator. A metallization structure is coupled to a sidewall surface of the epitaxial structure, and further coupled with one of the terminals of the first device.

公开(公告)号：US11430814B2

公开(公告)日：2022-08-30

申请号：US16957047

申请日：2018-03-05

Applicant: Intel Corporation

Inventor： Aaron D. Lilak ,  Anh Phan ,  Patrick Morrow ,  Willy Rachmady ,  Gilbert Dewey ,  Jessica M. Torres ,  Kimin Jun ,  Tristan A. Tronic ,  Christopher J. Jezewski ,  Hui Jae Yoo ,  Robert S. Chau ,  Chi-Hwa Tsang

IPC: H01L27/12 ,  H01L21/02 ,  H01L21/285 ,  H01L21/84 ,  H01L27/22 ,  H01L27/24 ,  H01L29/08 ,  H01L29/16 ,  H01L29/417 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78

Abstract: A stacked device structure includes a first device structure including a first body that includes a semiconductor material, and a plurality of terminals coupled with the first body. The stacked device structure further includes an insulator between the first device structure and a second device structure. The second device structure includes a second body such as a fin structure directly above the insulator. The second device structure further includes a gate coupled to the fin structure, a spacer including a dielectric material adjacent to the gate, and an epitaxial structure adjacent to a sidewall of the fin structure and between the spacer and the insulator. A metallization structure is coupled to a sidewall surface of the epitaxial structure, and further coupled with one of the terminals of the first device.

公开(公告)号：US20150371949A1

公开(公告)日：2015-12-24

申请号：US14841018

申请日：2015-08-31

Applicant: INTEL CORPORATION

Inventor： Daniel J. Zierath ,  Shaestagir Chowdhury ,  Chi-Hwa Tsang

IPC: H01L23/522

CPC classification number: H01L23/5226 ,  H01L21/76831 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76864 ,  H01L21/76874 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/485 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L23/5384 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Techniques are disclosed that enable interconnects, vias, metal gates, and other conductive features that can be formed through electroless material deposition techniques. In some embodiments, the techniques employ electroless fill in conjunction with high growth rate selectivity between an electroless nucleation material (ENM) and electroless suppression material (ESM) to generate bottom-up or otherwise desired fill pattern of such features. Suitable ENM may be present in the underlying or otherwise existing structure, or may be provided. The ESM is provisioned so as to prevent or otherwise inhibit nucleation at the ESM covered areas of the feature, which in turn prevents or otherwise slows down the rate of electroless growth on those areas. As such, the electroless growth rate on the ENM sites is higher than the electroless growth rate on the ESM sites.

Abstract translation: 公开了能够通过无电解材料沉积技术形成的互连，通孔，金属栅极和其它导电特征的技术。 在一些实施方案中，该技术采用无电填料结合无电成核材料（ENM）和无电压抑制材料（ESM）之间的高生长速率选择性，以产生这些特征的自下而上或其他期望的填充图案。 合适的ENM可能存在于底层或其他现有结构中，或可提供。 ESM的设置是为了防止或以其他方式抑制ESM覆盖的特征区域的成核，这又防止或以其他方式减缓这些区域的无电生长速率。 因此，ENM场地的无电增长率高于ESM站点上的无电增长率。