公开(公告)号：US20230223096A1

公开(公告)日：2023-07-13

申请号：US18122038

申请日：2023-03-15

Applicant: Intel Corporation

Inventor： Kuljit S. BAINS ,  Christopher P. MOZAK ,  Sagar SUTHRAM ,  Randy B. OSBORNE

IPC: G11C29/42 ,  G11C29/46 ,  G11C29/12

CPC classification number: G11C29/42 ,  G11C29/46 ,  G11C29/1201

Abstract: Methods and apparatus for configurable ECC (error correction code) mode in DRAM. Selected memory cells in the bank arrays of a DRAM device (e.g., die) are used to store ECC bits. A DRAM device (e.g., die) is configured to operate in a first mode in which an on-die ECC engine employs selected bits in the arrays of memory cells in the DRAM banks as ECC bits to perform ECC operations and to operate in a second mode under which the ECC bits are not employed for ECC operations by the ECC engine and made available for external use by a host. In the second mode, the repurposed ECC bits may comprise RAS bits used for RAS (Reliability, Serviceability, and Availability) operations and/or metabits comprising metadata used for other operations by the host.

公开(公告)号：US20230125041A1

公开(公告)日：2023-04-20

申请号：US18086584

申请日：2022-12-21

Applicant: Intel Corporation

Inventor： Christopher P. MOZAK ,  Sagar SUTHRAM ,  Randy B. OSBORNE ,  Don Douglas JOSEPHSON ,  Surhud KHARE

IPC: H10B80/00 ,  G11C11/408 ,  H01L23/528 ,  G06F12/06

Abstract: A memory chip stack is described. The memory chip stack includes memory chips having a first plurality of memory channels, where non-yielding ones of the memory channels are to be disabled during operation of the memory chip stack. The first plurality of memory channels have a second plurality of memory banks, where non-yielding ones of the memory banks within yielding ones of the memory channels are to be disabled during the operation of the memory chip stack.

公开(公告)号：US20220392519A1

公开(公告)日：2022-12-08

申请号：US17892000

申请日：2022-08-19

Applicant: Intel Corporation

Inventor： Randy B. OSBORNE ,  Christopher P. MOZAK ,  Shankar Ganesh RAMASUBRAMANIAN

IPC: G11C11/4093 ,  H01L25/065 ,  G11C11/4096 ,  G11C5/06

Abstract: Methods and apparatus for opportunistic full duplex DRAM for tightly coupled compute die and memory die. A memory controller includes one or more memory channel input-output (IO) interfaces having sets of read data (RdDQ) lines and write data (WrDQ) lines, and includes logic to implement concurrent read and write operations utilizing the RdDQ lines and WrDQ lines. A memory channel IO interface may be coupled to one or more memory devices such as DRAM DIMMs or DRAM/SDRAM dies having a mating IO interface, such as using through-silicon vias (TSVs) and die-to-die interconnects. Circuitry in a memory device or die includes a macro block of IO drivers coupled to the memory channel IO circuitry via a macro interface supporting full duplex operations. IO drivers in a macro block may be connected to memory banks using half-duplex bi-direction links to different banks or full duplex links to the same bank.

公开(公告)号：US20190172538A1

公开(公告)日：2019-06-06

申请号：US16172104

申请日：2018-10-26

Applicant: Intel Corporation

Inventor： Kumar K. Chinnaswamy ,  Randy B. OSBORNE ,  Erik W. Peter

IPC: G11C14/00 ,  G06F12/0866 ,  G06F12/08 ,  G11C7/10

Abstract: Methods and apparatuses for providing a hybrid memory module having both volatile and non-volatile memories to replace a DDR channel in a processing system.