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公开(公告)号:US20230140685A1
公开(公告)日:2023-05-04
申请号:US18089537
申请日:2022-12-27
Applicant: Intel Corporation
Inventor: Shrenik KOTHARI , Chandra Mohan JHA , Weihua TANG , Robert SANKMAN , Xavier BRUN , Pooya TADAYON
IPC: H01L23/42 , H01L23/522 , H01L23/373 , H01L23/367
Abstract: Embodiments disclosed herein include semiconductor dies and methods of forming such dies. In an embodiment, the semiconductor die comprises a semiconductor substrate, an active device layer in the semiconductor substrate, where the active device layer comprises one or more transistors, an interconnect layer over a first surface of the active device layer, a first bonding layer over a surface of the semiconductor substrate, a second bonding layer secured to the first bonding layer, and a heat spreader attached to the second bonding layer.
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公开(公告)号:US20240234245A1
公开(公告)日:2024-07-11
申请号:US18612949
申请日:2024-03-21
Applicant: Intel Corporation
Inventor: Shrenik KOTHARI , Chandra Mohan JHA , Weihua TANG , Robert SANKMAN , Xavier BRUN , Pooya TADAYON
IPC: H01L23/42 , H01L23/00 , H01L23/367 , H01L23/373 , H01L23/495 , H01L23/522 , H01L23/538 , H01L25/07
CPC classification number: H01L23/42 , H01L23/367 , H01L23/3738 , H01L23/522 , H01L23/49575 , H01L23/5384 , H01L24/20 , H01L25/072
Abstract: Embodiments disclosed herein include semiconductor dies and methods of forming such dies. In an embodiment, the semiconductor die comprises a semiconductor substrate, an active device layer in the semiconductor substrate, where the active device layer comprises one or more transistors, an interconnect layer over a first surface of the active device layer, a first bonding layer over a surface of the semiconductor substrate, a second bonding layer secured to the first bonding layer, and a heat spreader attached to the second bonding layer.
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公开(公告)号:US20210257272A1
公开(公告)日:2021-08-19
申请号:US16794815
申请日:2020-02-19
Applicant: Intel Corporation
Inventor: Shrenik KOTHARI , Arivindha ANTONISWAMY
IPC: H01L23/367 , H01L23/373
Abstract: Embodiments include semiconductor packages. A semiconductor package includes a first die and a second die on a package substrate, and an integrated heat spreader (IHS) over the first die, the second die, and the package substrate, wherein the IHS has a lid and a plurality of sidewalls. The semiconductor package also includes a plurality of conductive slugs in the lid of the IHS. The lid of the IHS has a bottom surface that is coplanar to bottom surfaces of the conductive slugs. The conductive slugs are comprised of high-k thermal conductive materials, including cubic boron nitride, hexagonal boron nitride, graphite, carbon-based materials, diamonds, or diamond-based materials. The bottom surfaces of the conductive slugs are on a top surface of the first die and a top surface of the second die. The IHS is comprised of thermal conductive materials, including aluminum, copper, copper-based metals, or alloys.
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公开(公告)号:US20210028087A1
公开(公告)日:2021-01-28
申请号:US16522443
申请日:2019-07-25
Applicant: Intel Corporation
Inventor: Shrenik KOTHARI , Chandra Mohan JHA , Weihau TANG , Robert SANKMAN , Xavier BRUN , Pooya TADAYON
IPC: H01L23/42 , H01L23/367 , H01L23/373 , H01L23/522
Abstract: Embodiments disclosed herein include semiconductor dies and methods of forming such dies. In an embodiment, the semiconductor die comprises a semiconductor substrate, an active device layer in the semiconductor substrate, where the active device layer comprises one or more transistors, an interconnect layer over a first surface of the active device layer, a first bonding layer over a surface of the semiconductor substrate, a second bonding layer secured to the first bonding layer, and a heat spreader attached to the second bonding layer.
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