公开(公告)号：US20210391244A1

公开(公告)日：2021-12-16

申请号：US16898196

申请日：2020-06-10

申请人： Intel Corporation

发明人： Chandra Mohan JHA ,  Pooya TADAYON ,  Aastha UPPAL ,  Weihua TANG ,  Paul DIGLIO ,  Xavier BRUN

IPC分类号： H01L23/498 ,  H01L23/373 ,  H01L23/522 ,  H01L21/56 ,  H01L21/78

摘要： Embodiments disclosed herein comprise a die and methods of forming a die. In an embodiment, a die comprises, a die substrate, wherein the die substrate has a first thermal conductivity, and a first layer over the die substrate, wherein the first layer has a second thermal conductivity that is greater than the first thermal conductivity. In an embodiment, the die further comprises a second layer over the first layer, wherein the second layer comprises transistors.

公开(公告)号：US20240234245A1

公开(公告)日：2024-07-11

申请号：US18612949

申请日：2024-03-21

申请人： Intel Corporation

发明人： Shrenik KOTHARI ,  Chandra Mohan JHA ,  Weihua TANG ,  Robert SANKMAN ,  Xavier BRUN ,  Pooya TADAYON

IPC分类号： H01L23/42 ,  H01L23/00 ,  H01L23/367 ,  H01L23/373 ,  H01L23/495 ,  H01L23/522 ,  H01L23/538 ,  H01L25/07

CPC分类号： H01L23/42 ,  H01L23/367 ,  H01L23/3738 ,  H01L23/522 ,  H01L23/49575 ,  H01L23/5384 ,  H01L24/20 ,  H01L25/072

摘要： Embodiments disclosed herein include semiconductor dies and methods of forming such dies. In an embodiment, the semiconductor die comprises a semiconductor substrate, an active device layer in the semiconductor substrate, where the active device layer comprises one or more transistors, an interconnect layer over a first surface of the active device layer, a first bonding layer over a surface of the semiconductor substrate, a second bonding layer secured to the first bonding layer, and a heat spreader attached to the second bonding layer.

公开(公告)号：US20210028087A1

公开(公告)日：2021-01-28

申请号：US16522443

申请日：2019-07-25

申请人： Intel Corporation

发明人： Shrenik KOTHARI ,  Chandra Mohan JHA ,  Weihau TANG ,  Robert SANKMAN ,  Xavier BRUN ,  Pooya TADAYON

IPC分类号： H01L23/42 ,  H01L23/367 ,  H01L23/373 ,  H01L23/522

摘要： Embodiments disclosed herein include semiconductor dies and methods of forming such dies. In an embodiment, the semiconductor die comprises a semiconductor substrate, an active device layer in the semiconductor substrate, where the active device layer comprises one or more transistors, an interconnect layer over a first surface of the active device layer, a first bonding layer over a surface of the semiconductor substrate, a second bonding layer secured to the first bonding layer, and a heat spreader attached to the second bonding layer.

公开(公告)号：US20240153837A1

公开(公告)日：2024-05-09

申请号：US17983226

申请日：2022-11-08

申请人： Intel Corporation

发明人： Ziyin LIN ,  Vipul MEHTA ,  Jonas CROISSANT ,  Jigneshkumar PATEL ,  Dingying XU ,  Gang DUAN ,  Aditya Sumanth YERRAMILLI ,  Suriyakala RAMALINGAM ,  Xavier BRUN

IPC分类号： H01L23/31 ,  H01L23/498 ,  H01L25/18

CPC分类号： H01L23/3157 ,  H01L23/49811 ,  H01L25/18 ,  H01L24/32 ,  H01L2224/32225

摘要： Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a die, and an array of pillars adjacent to the die. In an embodiment, the electronic package further comprises an underfill under the die, where an edge of the underfill is between an inner column of pillars in the array of pillars and an outer edge of the die, and where the edge of the underfill has a height that is less than a maximum height of the underfill.

公开(公告)号：US20230140685A1

公开(公告)日：2023-05-04

申请号：US18089537

申请日：2022-12-27

申请人： Intel Corporation

发明人： Shrenik KOTHARI ,  Chandra Mohan JHA ,  Weihua TANG ,  Robert SANKMAN ,  Xavier BRUN ,  Pooya TADAYON

IPC分类号： H01L23/42 ,  H01L23/522 ,  H01L23/373 ,  H01L23/367

摘要： Embodiments disclosed herein include semiconductor dies and methods of forming such dies. In an embodiment, the semiconductor die comprises a semiconductor substrate, an active device layer in the semiconductor substrate, where the active device layer comprises one or more transistors, an interconnect layer over a first surface of the active device layer, a first bonding layer over a surface of the semiconductor substrate, a second bonding layer secured to the first bonding layer, and a heat spreader attached to the second bonding layer.