公开(公告)号：US11789641B2

公开(公告)日：2023-10-17

申请号：US17349592

申请日：2021-06-16

Applicant: Intel Corporation

Inventor： Scott Weber ,  Jawad Khan ,  Ilya Ganusov ,  Martin Langhammer ,  Matthew Adiletta ,  Terence Magee ,  Albert Fazio ,  Richard Coulson ,  Ravi Gutala ,  Aravind Dasu ,  Mahesh Iyer

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/061 ,  G06F3/0673

Abstract: A three dimensional circuit system includes a first integrated circuit die having a core logic region that has first memory circuits and logic circuits. The three dimensional circuit system includes a second integrated circuit die that has second memory circuits. The first and second integrated circuit dies are coupled together in a vertically stacked configuration. The three dimensional circuit system includes third memory circuits coupled to the first integrated circuit die. The third memory circuits reside in a plane of the first integrated circuit die. The logic circuits are coupled to access the first, second, and third memory circuits and data can move between the first, second, and third memories. The third memory circuits have a larger memory capacity and a smaller memory access bandwidth than the second memory circuits. The second memory circuits have a larger memory capacity and a smaller memory access bandwidth than the first memory circuits.

公开(公告)号：US20230123826A1

公开(公告)日：2023-04-20

申请号：US18085528

申请日：2022-12-20

Applicant: Intel Corporation

Inventor： Terence Magee ,  Jeffrey Schulz

IPC: G11C7/22 ,  G11C7/10

Abstract: Systems or methods of the present disclosure may provide a programmable logic fabric and a memory controller communicatively coupled to the programmable logic fabric. The systems or methods also include a physical layer and IO circuit coupled to the programmable logic fabric via the memory controller and a FIFO to receive read data from a memory device coupled to the physical layer and IO circuit. Furthermore, the FIFO is closer to the memory controller than to the physical layer and IO circuit.

公开(公告)号：US20220405005A1

公开(公告)日：2022-12-22

申请号：US17349592

申请日：2021-06-16

Applicant: Intel Corporation

Inventor： Scott Weber ,  Jawad Khan ,  Ilya Ganusov ,  Martin Langhammer ,  Matthew Adiletta ,  Terence Magee ,  Albert Fazio ,  Richard Coulson ,  Ravi Gutala ,  Aravind Dasu ,  Mahesh Iyer

IPC: G06F3/06

Abstract: A three dimensional circuit system includes a first integrated circuit die having a core logic region that has first memory circuits and logic circuits. The three dimensional circuit system includes a second integrated circuit die that has second memory circuits. The first and second integrated circuit dies are coupled together in a vertically stacked configuration. The three dimensional circuit system includes third memory circuits coupled to the first integrated circuit die. The third memory circuits reside in a plane of the first integrated circuit die. The logic circuits are coupled to access the first, second, and third memory circuits and data can move between the first, second, and third memories. The third memory circuits have a larger memory capacity and a smaller memory access bandwidth than the second memory circuits. The second memory circuits have a larger memory capacity and a smaller memory access bandwidth than the first memory circuits.

公开(公告)号：US20230118912A1

公开(公告)日：2023-04-20

申请号：US18084158

申请日：2022-12-19

Applicant: Intel Corporation

Inventor： Jeffrey Schulz ,  Terence Magee

IPC: G11C7/22 ,  G06F3/06 ,  G11C7/10

Abstract: A memory interface circuit includes first and second memory controller circuits that asynchronously receive requests for memory accesses to first and second storage circuits. The memory interface circuit also includes first and second clock gate circuits that disable and then reenable first and second clock signals in response to a clock enable signal. The first and the second memory controller circuits perform the memory accesses to the first and the second storage circuits synchronously in response to the first and the second clock signals that have been reenabled by the first and the second clock gate circuits.

公开(公告)号：US20230140547A1

公开(公告)日：2023-05-04

申请号：US18091626

申请日：2022-12-30

Applicant: Intel Corporation

Inventor： Terence Magee ,  Jeffrey Schulz ,  Arun Patel

IPC: G06F13/16 ,  G06F11/10

Abstract: A system includes a programmable logic fabric core of an integrated circuit device and an IO interface communicatively coupled to the programmable logic fabric core. The IO interface includes multiple IO banks to implement a memory channel. Each IO bank includes a memory controller to control memory accesses of a memory device over the memory channel and multiple physical layer and IOs circuits to provide connections between the memory controller and the memory device. The respective memory controller may receive only a portion of data to be sent over the memory channel or multiple memory controllers may each receive all data to be sent over the memory channel.