中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

24 records (took 0.021 seconds)

    CONFIGURABLE MEMORY PROTECTION LEVELS PER REGION
    5.
    发明公开
    CONFIGURABLE MEMORY PROTECTION LEVELS PER REGION 审中-公开

    公开(公告)号：US20230185658A1

    公开(公告)日：2023-06-15

    申请号：US18108470

    申请日：2023-02-10

    Applicant: Intel Corporation

    Inventor： Duane Galbi ,  Matthew Adiletta

    IPC: G06F11/07 ,  G06F12/0811

    CPC classification number: G06F11/0793 ,  G06F11/073 ,  G06F12/0811 ,  G06F2212/601

    Abstract: An example of an electronic apparatus may comprise one or more substrates, and a controller coupled to the one or more substrates, the controller including circuitry to control access to a memory for a range of addresses within a memory address space, configure a first region of the memory within a first sub-range of addresses within the memory address space to be accessed with a first protection level of two or more memory fault protection levels, and configure a second region of the memory within a second sub-range of addresses within the memory address space that is non-overlapping with the first sub-range to be accessed with a second protection level of the two or more memory fault protection levels. Other examples are disclosed and claimed.

    Three Dimensional Circuit Systems And Methods Having Memory Hierarchies
    9.
    发明申请
    Three Dimensional Circuit Systems And Methods Having Memory Hierarchies 有权

    公开(公告)号：US20220405005A1

    公开(公告)日：2022-12-22

    申请号：US17349592

    申请日：2021-06-16

    Applicant: Intel Corporation

    Inventor： Scott Weber ,  Jawad Khan ,  Ilya Ganusov ,  Martin Langhammer ,  Matthew Adiletta ,  Terence Magee ,  Albert Fazio ,  Richard Coulson ,  Ravi Gutala ,  Aravind Dasu ,  Mahesh Iyer

    IPC: G06F3/06

    Abstract: A three dimensional circuit system includes a first integrated circuit die having a core logic region that has first memory circuits and logic circuits. The three dimensional circuit system includes a second integrated circuit die that has second memory circuits. The first and second integrated circuit dies are coupled together in a vertically stacked configuration. The three dimensional circuit system includes third memory circuits coupled to the first integrated circuit die. The third memory circuits reside in a plane of the first integrated circuit die. The logic circuits are coupled to access the first, second, and third memory circuits and data can move between the first, second, and third memories. The third memory circuits have a larger memory capacity and a smaller memory access bandwidth than the second memory circuits. The second memory circuits have a larger memory capacity and a smaller memory access bandwidth than the first memory circuits.

Patent Agency Ranking