公开(公告)号：US11106494B2

公开(公告)日：2021-08-31

申请号：US16147302

申请日：2018-09-28

申请人： Intel Corporation

发明人： Robert Pawlowski ,  Ankit More ,  Jason M. Howard ,  Joshua B. Fryman ,  Tina C. Zhong ,  Shaden Smith ,  Sowmya Pitchaimoorthy ,  Samkit Jain ,  Vincent Cave ,  Sriram Aananthakrishnan ,  Bharadwaj Krishnamurthy

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F9/48 ,  G06F12/0815 ,  G06F9/35 ,  G06F13/28

摘要： Disclosed embodiments relate to an improved memory system architecture for multi-threaded processors. In one example, a system includes a system comprising a multi-threaded processor core (MTPC), the MTPC comprising: P pipelines, each to concurrently process T threads; a crossbar to communicatively couple the P pipelines; a memory for use by the P pipelines, a scheduler to optimize reduction operations by assigning multiple threads to generate results of commutative arithmetic operations, and then accumulate the generated results, and a memory controller (MC) to connect with external storage and other MTPCs, the MC further comprising at least one optimization selected from: an instruction set architecture including a dual-memory operation; a direct memory access (DMA) engine; a buffer to store multiple pending instruction cache requests; multiple channels across which to stripe memory requests; and a shadow-tag coherency management unit.

公开(公告)号：US11630691B2

公开(公告)日：2023-04-18

申请号：US17410818

申请日：2021-08-24

申请人： Intel Corporation

发明人： Robert Pawlowski ,  Ankit More ,  Jason M. Howard ,  Joshua B. Fryman ,  Tina C. Zhong ,  Shaden Smith ,  Sowmya Pitchaimoorthy ,  Samkit Jain ,  Vincent Cave ,  Sriram Aananthakrishnan ,  Bharadwaj Krishnamurthy

IPC分类号： G06F9/30 ,  G06F9/35 ,  G06F9/48 ,  G06F12/0815 ,  G06F9/38 ,  G06F13/28

摘要： Disclosed embodiments relate to an improved memory system architecture for multi-threaded processors. In one example, a system includes a system comprising a multi-threaded processor core (MTPC), the MTPC comprising: P pipelines, each to concurrently process T threads; a crossbar to communicatively couple the P pipelines; a memory for use by the P pipelines, a scheduler to optimize reduction operations by assigning multiple threads to generate results of commutative arithmetic operations, and then accumulate the generated results, and a memory controller (MC) to connect with external storage and other MTPCs, the MC further comprising at least one optimization selected from: an instruction set architecture including a dual-memory operation; a direct memory access (DMA) engine; a buffer to store multiple pending instruction cache requests; multiple channels across which to stripe memory requests; and a shadow-tag coherency management unit.

公开(公告)号：US20190095224A1

公开(公告)日：2019-03-28

申请号：US15719340

申请日：2017-09-28

申请人： Intel Corporation

发明人： Tina C. Zhong ,  Russell J. Wunderlich ,  Chih-Cheh Chen ,  Malay Trivedi

IPC分类号： G06F9/44 ,  G06F1/24

摘要： Embodiments disclosed herein relate to coordinated system boot and reset flows and improve reliability, availability, and serviceability (RAS) among multiple chipsets. In an example, a system includes a master chipset having multiple interfaces, each interface to connect to one of a processor and a chipset, at least one processor connected to the master chipset, at least one non-master chipset connected to the master chipset, and a sideband messaging channel connecting the master chipset and the non-master chipsets, wherein the master chipset is to probe a subset of its multiple interfaces to discover a topology of connected processors and non-master chipsets, and use the sideband messaging channel to coordinate a synchronized boot flow.

公开(公告)号：US20190004989A1

公开(公告)日：2019-01-03

申请号：US15639035

申请日：2017-06-30

申请人： INTEL CORPORATION

发明人： Chih-Cheh Chen ,  Russell J. Wunderlich ,  Tina C. Zhong

IPC分类号： G06F13/40

摘要： Examples may include chipsets, processor circuits, and a system including chipsets and processor circuits. The chipsets and processor circuits can be coupled together via side band interconnect. The chipsets and processor circuits can be coupled together dynamically, during runtime using the side band interconnects. A chipset can send control signals for other chipsets and/or receive control signals from processor circuits via the side band links to dynamically coordinate the chipsets and processor circuits into systems.

公开(公告)号：US10929330B2

公开(公告)日：2021-02-23

申请号：US15639035

申请日：2017-06-30

申请人： INTEL CORPORATION

发明人： Chih-Cheh Chen ,  Russell J. Wunderlich ,  Tina C. Zhong

IPC分类号： G06F13/40

摘要： Examples may include chipsets, processor circuits, and a system including chipsets and processor circuits. The chipsets and processor circuits can be coupled together via side band interconnect. The chipsets and processor circuits can be coupled together dynamically, during runtime using the side band interconnects. A chipset can send control signals for other chipsets and/or receive control signals from processor circuits via the side band links to dynamically coordinate the chipsets and processor circuits into systems.

公开(公告)号：US08799728B2

公开(公告)日：2014-08-05

申请号：US14063549

申请日：2013-10-25

申请人： Intel Corporation

发明人： Tina C. Zhong ,  Jason G. Sandri ,  Kenneth P. Griesser ,  Lori R. Borger

IPC分类号： G01R31/28 ,  G06F13/00 ,  G01R31/26 ,  G01R31/3177 ,  G01R31/317 ,  G01R31/3185 ,  G01R31/319 ,  G06F11/25 ,  G06F11/36 ,  G06F11/30

CPC分类号： G01R31/3177 ,  G01R31/31705 ,  G01R31/318511 ,  G01R31/318513 ,  G01R31/319 ,  G06F11/079 ,  G06F11/25 ,  G06F11/3003 ,  G06F11/3089 ,  G06F11/364 ,  G06F11/3648

摘要： In one embodiment, the present invention includes a semiconductor die such as a system on a chip (SoC) that includes a logic analyzer with a built-in trace buffer to store information communicated between on-die agents at speed and to provide the information to an off-die agent at a slower speed. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，本发明包括诸如片上系统（SoC）的半导体管芯，其包括具有内置跟踪缓冲器的逻辑分析器，用于存储在速度上在管芯代理之间传送的信息，并将信息提供给 较低速度的脱模剂。 描述和要求保护其他实施例。

公开(公告)号：US08543776B2

公开(公告)日：2013-09-24

申请号：US13665198

申请日：2012-10-31

申请人： Intel Corporation

发明人： Tina C. Zhong ,  Jason G. Sandri ,  Kenneth P. Griesser ,  Lori R. Borger

IPC分类号： G06F12/00 ,  G06F13/28 ,  G06F3/00 ,  G01R31/28

CPC分类号： G01R31/3177 ,  G01R31/31705 ,  G01R31/318511 ,  G01R31/318513 ,  G01R31/319 ,  G06F11/079 ,  G06F11/25 ,  G06F11/3003 ,  G06F11/3089 ,  G06F11/364 ,  G06F11/3648

摘要： In one embodiment, the present invention includes a semiconductor die such as a system on a chip (SoC) that includes a logic analyzer with a built-in trace buffer to store information communicated between on-die agents at speed and to provide the information to an off-die agent at a slower speed. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，本发明包括诸如片上系统（SoC）的半导体管芯，其包括具有内置跟踪缓冲器的逻辑分析器，用于存储在速度上在管芯代理之间传送的信息，并将信息提供给 较低速度的脱模剂。 描述和要求保护其他实施例。