公开(公告)号：US10929330B2

公开(公告)日：2021-02-23

申请号：US15639035

申请日：2017-06-30

Applicant: INTEL CORPORATION

Inventor： Chih-Cheh Chen ,  Russell J. Wunderlich ,  Tina C. Zhong

IPC: G06F13/40

Abstract: Examples may include chipsets, processor circuits, and a system including chipsets and processor circuits. The chipsets and processor circuits can be coupled together via side band interconnect. The chipsets and processor circuits can be coupled together dynamically, during runtime using the side band interconnects. A chipset can send control signals for other chipsets and/or receive control signals from processor circuits via the side band links to dynamically coordinate the chipsets and processor circuits into systems.

公开(公告)号：US10817454B2

公开(公告)日：2020-10-27

申请号：US16396153

申请日：2019-04-26

Applicant: Intel Corporation

Inventor： Chih-Cheh Chen ,  Janusz P. Jurski ,  Amit Kumar Srivastava ,  Malay Trivedi ,  James Mitchell ,  Piotr Michael Kwidzinski ,  David N. Lombard

IPC: G06F13/40 ,  G06F13/42 ,  G06F1/329 ,  G06F1/3234 ,  G06F9/38 ,  G06F1/3228

Abstract: An apparatus includes physical layer circuitry with lanes to couple the apparatus to endpoint devices. a first input/output (I/O) controller to couple a first processor to the physical layer circuitry, and a second I/O controller to couple a second processor to the physical layer circuitry. The first and second I/O controllers are compatible with a Peripheral Component Interconnect Express (PCIe)-based protocol. The apparatus also includes a flexible input/output adapter (FIA) coupling the first and second I/O controllers to the lanes. The FIA selectively assigns access to each lane of the lanes by either the first or second I/O controller. The apparatus also includes a power management controller (PMC) communicably coupled to the FIA. The PMC causes the FIA to dynamically assign access to at least one of the lanes by the first or second I/O controller without a reboot cycle.

公开(公告)号：US20190251055A1

公开(公告)日：2019-08-15

申请号：US16396153

申请日：2019-04-26

Applicant: Intel Corporation

Inventor： Chih-Cheh Chen ,  Janusz P. Jurski ,  Amit Kumar Srivastava ,  Malay Trivedi ,  James Mitchell ,  Piotr Michael Kwidzinski ,  David N. Lombard

IPC: G06F13/40 ,  G06F13/42 ,  G06F1/329 ,  G06F1/3228 ,  G06F1/3234 ,  G06F9/38

CPC classification number: G06F13/4068 ,  G06F1/3228 ,  G06F1/3253 ,  G06F1/329 ,  G06F9/3877 ,  G06F13/4221 ,  G06F2212/1028

Abstract: An apparatus includes physical layer circuitry with lanes to couple the apparatus to endpoint devices. a first input/output (I/O) controller to couple a first processor to the physical layer circuitry, and a second I/O controller to couple a second processor to the physical layer circuitry. The first and second I/O controllers are compatible with a Peripheral Component Interconnect Express (PCIe)-based protocol. The apparatus also includes a flexible input/output adapter (FIA) coupling the first and second I/O controllers to the lanes. The FIA selectively assigns access to each lane of the lanes by either the first or second I/O controller. The apparatus also includes a power management controller (PMC) communicably coupled to the FIA. The PMC causes the FIA to dynamically assign access to at least one of the lanes by the first or second I/O controller without a reboot cycle.

公开(公告)号：US20190095224A1

公开(公告)日：2019-03-28

申请号：US15719340

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Tina C. Zhong ,  Russell J. Wunderlich ,  Chih-Cheh Chen ,  Malay Trivedi

IPC: G06F9/44 ,  G06F1/24

Abstract: Embodiments disclosed herein relate to coordinated system boot and reset flows and improve reliability, availability, and serviceability (RAS) among multiple chipsets. In an example, a system includes a master chipset having multiple interfaces, each interface to connect to one of a processor and a chipset, at least one processor connected to the master chipset, at least one non-master chipset connected to the master chipset, and a sideband messaging channel connecting the master chipset and the non-master chipsets, wherein the master chipset is to probe a subset of its multiple interfaces to discover a topology of connected processors and non-master chipsets, and use the sideband messaging channel to coordinate a synchronized boot flow.

公开(公告)号：US20190004989A1

公开(公告)日：2019-01-03

申请号：US15639035

申请日：2017-06-30

Applicant: INTEL CORPORATION

Inventor： Chih-Cheh Chen ,  Russell J. Wunderlich ,  Tina C. Zhong

IPC: G06F13/40

Abstract: Examples may include chipsets, processor circuits, and a system including chipsets and processor circuits. The chipsets and processor circuits can be coupled together via side band interconnect. The chipsets and processor circuits can be coupled together dynamically, during runtime using the side band interconnects. A chipset can send control signals for other chipsets and/or receive control signals from processor circuits via the side band links to dynamically coordinate the chipsets and processor circuits into systems.