公开(公告)号：US20190086727A1

公开(公告)日：2019-03-21

申请号：US15711014

申请日：2017-09-21

Applicant: INTEL CORPORATION

Inventor： Vijayakumar A. Dibbad ,  Mallari C. Hanchate

IPC: G02F1/1335 ,  G09G3/34 ,  G09G3/3258

Abstract: In some examples, display backlight strings are grouped into at least two groups based on characteristics of the display backlight strings. A first of the at least two groups of display backlight strings is operated at a first operating voltage. A second of the at least two groups of display backlight strings is operated at a second operating voltage.

公开(公告)号：US10732683B2

公开(公告)日：2020-08-04

申请号：US15967116

申请日：2018-04-30

Applicant: Intel Corporation

Inventor： Sachin Bedare ,  Mallari Hanchate ,  Praveen Kashyap Ananta Bhat ,  Govindaraj Gettimalli ,  Vijayakumar A. Dibbad

IPC: G06F1/26 ,  G06F1/32 ,  G06F1/3234 ,  G06F1/3287

Abstract: In some embodiments, power may be temporarily removed from a first portion of a computer system (such as a display), and that power redirected to a second portion (such as a processor or System on a Chip), so that extra performance may be obtained from the second portion without exceeding the power budget for the system. If the first portion is a display, the time period of removed power may be short enough that the absence of luminance during that time period will not be noticeable to the human vision system. In a similar embodiment, power may be delivered to the first portion using pulse width modulation, using the time between pulses to redirect power to the other portion.

公开(公告)号：US20190041931A1

公开(公告)日：2019-02-07

申请号：US15967116

申请日：2018-04-30

Applicant: Intel Corporation

Inventor： Sachin Bedare ,  Mallari Hanchate ,  Praveen Kashyap Ananta Bhat ,  Govindaraj Gettimalli ,  Vijayakumar A. Dibbad

IPC: G06F1/26

Abstract: In some embodiments, power may be temporarily removed from a first portion of a computer system (such as a display), and that power redirected to a second portion (such as a processor or System on a Chip), so that extra performance may be obtained from the second portion without exceeding the power budget for the system. If the first portion is a display, the time period of removed power may be short enough that the absence of luminance during that time period will not be noticeable to the human vision system. In a similar embodiment, power may be delivered to the first portion using pulse width modulation, using the time between pulses to redirect power to the other portion.

公开(公告)号：US10551900B2

公开(公告)日：2020-02-04

申请号：US15471606

申请日：2017-03-28

Applicant: Intel Corporation

Inventor： Vijayakumar A. Dibbad ,  Satish Prathaban ,  Harinarayanan Seshadri ,  Rajeev D. Muralidhar

IPC: G06F1/324 ,  G06F1/3228 ,  G06F1/329

Abstract: A first optimal CPU frequency that produces minimal power consumption for a CPU/platform combination may be calculated by using an Efficiency Aware Race to Halt (EARtH) algorithm, which ignores the power efficiency curve of the voltage regulator (VR). These results may then be modified by applying the power efficiency curve of the associated VR to determine a second optimal CPU frequency that produces power consumption that is less than the value calculated by the EARtH algorithm.

公开(公告)号：US20180284863A1

公开(公告)日：2018-10-04

申请号：US15471606

申请日：2017-03-28

Applicant: Intel Corporation

Inventor： Vijayakumar A. Dibbad ,  Satish Prathaban ,  Harinarayanan Seshadri ,  Rajeev D. Muralidhar

IPC: G06F1/32

CPC classification number: G06F1/324 ,  G06F1/3228 ,  G06F1/329

Abstract: A first optimal CPU frequency that produces minimal power consumption for a CPU/platform combination may be calculated by using an Efficiency Aware Race to Halt (EARtH) algorithm, which ignores the power efficiency curve of the voltage regulator (VR). These results may then be modified by applying the power efficiency curve of the associated VR to determine a second optimal CPU frequency that produces power consumption that is less than the value calculated by the EARtH algorithm.