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    Phased boot process to dynamically initialize devices in a verified environment
    2.
    发明授权
    Phased boot process to dynamically initialize devices in a verified environment 有权

    公开(公告)号：US11816220B2

    公开(公告)日：2023-11-14

    申请号：US17032369

    申请日：2020-09-25

    Applicant: Intel Corporation

    Inventor： Rajaram Regupathy ,  Subrata Banik ,  Vincent Zimmer ,  Saranya Gopal

    IPC: G06F21/57 ,  G06F21/79

    CPC classification number: G06F21/575 ,  G06F21/572 ,  G06F21/79

    Abstract: Embodiments are directed to a phased boot process to dynamically initialize devices in a verified environment. An embodiment of a system includes a memory device to store platform initialization firmware to cause the processing system to: initialize, during a boot process, a portion of the one or more memory modules as system management random access memory (SMRAM) for system management mode (SMM) usage; generate an SMM component in the SMRAM, the SMM component comprising an SMM handler routine to handle dynamic intellectual property (IP) management operations corresponding to the plurality of hardware components; register the SMM handler routine with an SMM interrupt (SMI) for identification of SMM events from an operating system (OS); and generate an SMM dispatcher in the SMRAM, the SMM dispatcher to create an instance of the SMM handler routine in the SMRAM in response to receiving an SMI from the OS during runtime of the processing system.

    METHODS AND APPARATUS TO CONDITIONALLY ACTIVATE A BIG CORE IN A COMPUTING SYSTEM
    4.
    发明申请
    METHODS AND APPARATUS TO CONDITIONALLY ACTIVATE A BIG CORE IN A COMPUTING SYSTEM 有权

    公开(公告)号：US20220113978A1

    公开(公告)日：2022-04-14

    申请号：US17560025

    申请日：2021-12-22

    Applicant: Intel Corporation

    Inventor： Rajesh Poornachandran ,  Vincent Zimmer

    IPC: G06F9/38 ,  G06F9/455 ,  G06F21/54

    Abstract: Methods, apparatus, and articles of manufacture to conditionally activate a big core in a computing system are disclosed. An example apparatus including instructions stored in the apparatus; and processor circuitry to execute the instructions to: in response to a request to operate two or more processing devices as a single processing device, determine whether the two or more processing devices are available and capable of executing instructions according to the request; when the two or more processing devices are available and capable: split the instructions into first sub-instructions and second sub-instructions; provide (a) the first sub-instructions to a first processing device of the two or more processing devices and (b) the second sub-instructions to a second processing device of the two or more processing devices; and generate an output by combining a first output of the first processing device and a second output of the second processing device.

    METHODS AND APPARATUS TO INCREASE BOOT PERFORMANCE
    5.
    发明申请
    METHODS AND APPARATUS TO INCREASE BOOT PERFORMANCE 有权

    公开(公告)号：US20220012062A1

    公开(公告)日：2022-01-13

    申请号：US17482201

    申请日：2021-09-22

    Applicant: Intel Corporation

    Inventor： Subrata Banik ,  Rajaram Regupathy ,  Vincent Zimmer ,  Julius Mandelblat

    IPC: G06F9/4401 ,  G06F11/34

    Abstract: Methods, apparatus, systems, and articles of manufacture to increase boot performance are disclosed. An example apparatus including instructions stored in the apparatus; and processor circuitry to execute the instructions to: during a boot process: identify a boot task that is to be performed during the boot process; execute the boot task using a first processor component; collect data corresponding to the execution of the boot task on the first processor component; categorize the boot task based on the collected data; and generate an entry for a boot table based on the categorization, the boot table used to schedule the boot task on at least one of the first processor component or a second processor component different than the first processor component based on the categorization.

    APPLICATION AWARE GRACEFUL OVER CURRENT PROTECTION FOR MULTI-SOCKET PLATFORMS
    6.
    发明申请
    APPLICATION AWARE GRACEFUL OVER CURRENT PROTECTION FOR MULTI-SOCKET PLATFORMS 有权

    公开(公告)号：US20210141665A1

    公开(公告)日：2021-05-13

    申请号：US17122693

    申请日：2020-12-15

    Applicant: Intel Corporation

    Inventor： Rajesh Poornachandran ,  Rajendrakumar Chinnaiyan ,  Vincent Zimmer ,  Ravikiran Chukka

    IPC: G06F9/48 ,  G06F1/30 ,  G06F9/455 ,  H02H1/00 ,  G05F1/625

    Abstract: Systems, apparatuses and methods may provide for technology that detects an over current condition associated with a voltage regulator in a computing system, identifies a configurable over current protection policy associated with the voltage regulator, and automatically takes a protective action based on the configurable over current protection policy. In one example, the protective action includes one or more of a frequency throttle of a processor coupled to the voltage regulator in isolation from one or more additional processors in the computing system, a deactivation of the processor in isolation from the one or more additional processors, an issuance of a virtual machine monitor notification, an issuance of a data center fleet manager notification, or an initiation of a migration of a workload from the processor to at least one of the additional processor(s).

    PHASED BOOT PROCESS TO DYNAMICALLY INITIALIZE DEVICES IN A VERIFIED ENVIRONMENT
    7.
    发明申请
    PHASED BOOT PROCESS TO DYNAMICALLY INITIALIZE DEVICES IN A VERIFIED ENVIRONMENT 有权

    公开(公告)号：US20210019420A1

    公开(公告)日：2021-01-21

    申请号：US17032369

    申请日：2020-09-25

    Applicant: Intel Corporation

    Inventor： Rajaram Regupathy ,  Subrata Banik ,  Vincent Zimmer ,  Saranya Gopal

    IPC: G06F21/57 ,  G06F21/79 ,  G06F9/48 ,  G06F9/54

    Abstract: Embodiments are directed to a phased boot process to dynamically initialize devices in a verified environment. An embodiment of a system includes a memory device to store platform initialization firmware to cause the processing system to: initialize, during a boot process, a portion of the one or more memory modules as system management random access memory (SMRAM) for system management mode (SMM) usage; generate an SMM component in the SMRAM, the SMM component comprising an SMM handler routine to handle dynamic intellectual property (IP) management operations corresponding to the plurality of hardware components; register the SMM handler routine with an SMM interrupt (SMI) for identification of SMM events from an operating system (OS); and generate an SMM dispatcher in the SMRAM, the SMM dispatcher to create an instance of the SMM handler routine in the SMRAM in response to receiving an SMI from the OS during runtime of the processing system.

    Controlled customization of silicon initialization
    8.
    发明授权
    Controlled customization of silicon initialization 有权

    公开(公告)号：US10310865B2

    公开(公告)日：2019-06-04

    申请号：US15100267

    申请日：2013-12-27

    Applicant: Intel Corporation

    Inventor： Jiewen Yao ,  Vincent Zimmer ,  Nicholas Adams ,  Willard Wiseman ,  Giri Mudusuru ,  Nuo Zhang

    IPC: G06F9/00 ,  G06F15/177 ,  G06F9/4401 ,  G06F9/445 ,  G06F21/57

    Abstract: The present disclosure is directed to controlled customization of silicon initialization. A device may comprise, for example, a boot module including a memory on which boot code is stored, the boot code including at least an initial boot block (IBB) module that is not customizable and a global platform database (GPD) module including customizable data. The IBB module may include a pointer indicating GPD module location. The customizable data may comprise configurable parameters and simple configuration language (SCL) to cause the device to execute at least one logical operation during execution of the boot code. The GPD module may further comprise a pointer indicating SCL location. The boot code may be executed upon activation of the device, which may cause the IBB module to load an interpreter for executing the SCL. The interpreter may also verify access request operations in the SCL are valid before executing the access request operations.

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