公开(公告)号：US10199091B2

公开(公告)日：2019-02-05

申请号：US15373048

申请日：2016-12-08

Applicant: Intel Corporation

Inventor： Minki Cho ,  Jaydeep Kulkarni ,  Carlos Tokunaga ,  Muhammad Khellah ,  James Tschanz

IPC: G11C5/14 ,  G11C11/417 ,  G11C11/413 ,  G11C29/24 ,  G11C29/04 ,  G11C29/12 ,  G11C29/52 ,  G11C11/412 ,  G11C29/50

Abstract: An apparatus is described. The apparatus includes a semiconductor chip. The semiconductor chip includes a memory having multiple storage cells. The storage cells are to receive a supply voltage. The semiconductor chip includes supply voltage retention circuitry. The supply voltage retention circuitry is to determine a level of the supply voltage at which the storage cells are able to retain their respective data. The supply voltage retention circuitry is to receive the supply voltage during a stress mode of the supply voltage retention circuitry. The supply voltage retention circuitry is to more weakly retain its stored information than the storage cells during a measurement mode at which the level is determined.

公开(公告)号：US20170243637A1

公开(公告)日：2017-08-24

申请号：US15495954

申请日：2017-04-24

Applicant: Intel Corporation

Inventor： Jaydeep P. Kulkarni ,  Bibiche M. Geuskens ,  James Tschanz ,  Vivek K. De ,  Muhammed M. Khellah

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C5/14 ,  G11C5/145 ,  G11C5/147 ,  G11C5/148 ,  G11C7/12 ,  G11C8/08 ,  G11C8/10 ,  G11C11/4074 ,  G11C11/412 ,  G11C11/417 ,  G11C11/418 ,  G11C13/0038 ,  G11C29/021 ,  G11C29/028 ,  G11C2207/2227

Abstract: Methods and systems to provide a multi-Vcc environment, such as to selectively boost an operating voltage of a logic block and/or provide a level-shifted control to the logic block. A multi-Vcc environment may be implemented to isolate a Vmin-limiting logic block from a single-Vcc environment, such as to reduce Vmin and/or improve energy efficiency in the single-Vcc environment. The logic block may include bit cells of a register file, a low-level processor cache, and/or other memory system. A cell Vcc may be boosted during a read mode and/or write wordlines (WWLs) and/or read wordlines (RWLs) may be asserted with boost. A wordline decoder may include a voltage level shifter with differential split-level logic, and a dynamic NAND, which may include NAND logic, a keeper circuit, and logic to delay a keeper control based on a delay of the level shifter to reduce contention during an initial NAND evaluation phase.

公开(公告)号：US20180287592A1

公开(公告)日：2018-10-04

申请号：US15477913

申请日：2017-04-03

Applicant: Intel Corporation

Inventor： Minki Cho ,  Jaydeep Kulkarni ,  Carlos Tokunaga ,  Muhammad Khellah ,  James Tschanz

IPC: H03K3/011 ,  H03K3/012 ,  G11C11/419 ,  G06F1/32

CPC classification number: H03K3/011 ,  G06F1/3275 ,  G11C11/413 ,  G11C11/419 ,  G11C29/04 ,  H03K3/012

Abstract: An apparatus is provided which includes: a first power supply node; a second power supply node; a memory bit-cell coupled to the second power supply node; a circuitry coupled to the first and second power supply nodes, the circuitry to operate in a diode-connected mode; and a transistor coupled in parallel to the circuitry, wherein the transistor is controllable by a digital signal such that when the transistor is to turn on, it is to apply voltage and/or current stress to the memory bit-cell.

公开(公告)号：US12237832B2

公开(公告)日：2025-02-25

申请号：US17479963

申请日：2021-09-20

Applicant: Intel Corporation

Inventor： Miguel Bautista Gabriel ,  Sriram Vangal ,  Patrick Koeberl ,  Pratik Patel ,  Muhammad Khellah ,  James Tschanz ,  Carlos Tokunaga ,  Suyoung Bang

IPC: H03K19/177 ,  G01R31/28 ,  H03K19/0175 ,  H03K19/0185 ,  H03K19/17768 ,  H03K19/17784

Abstract: A detection circuit includes a tunable delay circuit that generates a delayed signal and that receives a supply voltage. The detection circuit includes a control circuit that adjusts a delay provided by the tunable delay circuit to the delayed signal. The detection circuit includes a time-to-digital converter circuit that converts the delay provided by the tunable delay circuit to the delayed signal to a digital code and adjusts the digital code based on changes in the supply voltage. The control circuit causes the tunable delay circuit to maintain the delay provided to the delayed signal constant in response to the digital code reaching an alignment value. The detection circuit may continuously monitor timing margin of a data signal relative to a clock signal and update the digital code in every clock cycle. The detection circuit may be a security sensor that detects changes in the supply voltage.

公开(公告)号：US11828776B2

公开(公告)日：2023-11-28

申请号：US16829582

申请日：2020-03-25

Applicant: Intel Corporation

Inventor： Pratik Patel ,  Sriram Vangal ,  Patrick Koeberl ,  Miguel Bautista Gabriel ,  James Tschanz ,  Carlos Tokunaga

IPC: G01R19/165 ,  G06F21/75 ,  H03K5/00 ,  H03K3/037 ,  H03K19/21 ,  H01L23/00 ,  G06F11/07

CPC classification number: G01R19/16533 ,  G06F11/0736 ,  G06F11/0757 ,  G06F11/0772 ,  G06F21/755 ,  H01L23/576 ,  H03K3/037 ,  H03K5/00 ,  H03K19/21 ,  H03K2005/00058 ,  H03K2005/00078

Abstract: A voltage detection circuit includes a tunable delay circuit that receives a supply voltage and that generates a delayed signal in response to an input signal. A control circuit causes a first adjustment in a delay provided by the tunable delay circuit to the delayed signal. An error detection circuit generates an error indication in an error signal in response to a change in a timing of the delayed signal relative to a clock signal caused by the first adjustment in the delay provided to the delayed signal. The control circuit causes a second adjustment in the delay provided by the tunable delay circuit to the delayed signal in response to the error indication. The error detection circuit causes the error signal to be indicative of the supply voltage reaching a threshold voltage after the second adjustment in the delay.

公开(公告)号：US10984855B2

公开(公告)日：2021-04-20

申请号：US16285057

申请日：2019-02-25

Applicant: Intel Corporation

Inventor： Jaydeep P. Kulkarni ,  Bibiche M. Geuskens ,  James Tschanz ,  Vivek K. De ,  Muhammed M. Khellah

IPC: G11C11/419 ,  G11C5/14 ,  G11C7/12 ,  G11C8/10 ,  H01L27/11 ,  G11C7/08 ,  G11C11/4074 ,  G11C11/412 ,  G11C11/417 ,  G11C11/418 ,  G11C13/00 ,  G11C29/02 ,  G11C8/08

Abstract: Methods and systems to provide a multi-Vcc environment, such as to selectively boost an operating voltage of a logic block and/or provide a level-shifted control to the logic block. A multi-Vcc environment may be implemented to isolate a Vmin-limiting logic block from a single-Vcc environment, such as to reduce Vmin and/or improve energy efficiency in the single-Vcc environment. The logic block may include bit cells of a register file, a low-level processor cache, and/or other memory system. A cell Vcc may be boosted during a read mode and/or write wordlines (WWLs) and/or read wordlines (RWLs) may be asserted with boost. A wordline decoder may include a voltage level shifter with differential split-level logic, and a dynamic NAND, which may include NAND logic, a keeper circuit, and logic to delay a keeper control based on a delay of the level shifter to reduce contention during an initial NAND evaluation phase.

公开(公告)号：US20210116982A1

公开(公告)日：2021-04-22

申请号：US17133226

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Rahul Khanna ,  Xin Kang ,  Ali Taha ,  James Tschanz ,  William Zand ,  Robert Kwasnick

IPC: G06F1/324 ,  G06F1/3296 ,  G06F1/3287 ,  G06F9/50

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to optimize a guard band of a hardware resource. An example apparatus includes at least one storage device, and at least one processor to execute instructions to identify a phase of a workload based on an output from a machine-learning model, the phase based on a utilization of one or more hardware resources, and based on the phase, control a guard band of a first hardware resource of the one or more hardware resources.

公开(公告)号：US20200226295A1

公开(公告)日：2020-07-16

申请号：US16829582

申请日：2020-03-25

Applicant: Intel Corporation

Inventor： Pratik Patel ,  Sriram Vangal ,  Patrick Koeberl ,  Miguel Bautista Gabriel ,  James Tschanz ,  Carlos Tokunaga

IPC: G06F21/75 ,  H03K5/00 ,  H03K3/037 ,  H03K19/21 ,  H01L23/00 ,  G06F11/07 ,  G01R19/165

Abstract: A voltage detection circuit includes a tunable delay circuit that receives a supply voltage and that generates a delayed signal in response to an input signal. A control circuit causes a first adjustment in a delay provided by the tunable delay circuit to the delayed signal. An error detection circuit generates an error indication in an error signal in response to a change in a timing of the delayed signal relative to a clock signal caused by the first adjustment in the delay provided to the delayed signal. The control circuit causes a second adjustment in the delay provided by the tunable delay circuit to the delayed signal in response to the error indication. The error detection circuit causes the error signal to be indicative of the supply voltage reaching a threshold voltage after the second adjustment in the delay.

公开(公告)号：US20160225438A1

公开(公告)日：2016-08-04

申请号：US14989762

申请日：2016-01-06

Applicant: Intel Corporation

Inventor： Jaydeep P. Kulkarni ,  Bibiche M. Geuskens ,  James Tschanz ,  Vivek K. De ,  Muhammed M. Khellah

IPC: G11C11/419 ,  G11C5/14 ,  G11C7/12 ,  G11C11/418 ,  G11C8/10

CPC classification number: G11C11/419 ,  G11C5/14 ,  G11C5/145 ,  G11C5/147 ,  G11C5/148 ,  G11C7/12 ,  G11C8/08 ,  G11C8/10 ,  G11C11/4074 ,  G11C11/412 ,  G11C11/417 ,  G11C11/418 ,  G11C13/0038 ,  G11C29/021 ,  G11C29/028 ,  G11C2207/2227

Abstract: Methods and systems to provide a multi-Vcc environment, such as to selectively boost an operating voltage of a logic block and/or provide a level-shifted control to the logic block. A multi-Vcc environment may be implemented to isolate a Vmin-limiting logic block from a single-Vcc environment, such as to reduce Vmin and/or improve energy efficiency in the single-Vcc environment. The logic block may include bit cells of a register file, a low-level processor cache, and/or other memory system. A cell Vcc may be boosted during a read mode and/or write wordlines (WWLs) and/or read wordlines (RWLs) may be asserted with boost. A wordline decoder may include a voltage level shifter with differential split-level logic, and a dynamic NAND, which may include NAND logic, a keeper circuit, and logic to delay a keeper control based on a delay of the level shifter to reduce contention during an initial NAND evaluation phase.

公开(公告)号：US12130688B2

公开(公告)日：2024-10-29

申请号：US17133226

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Rahul Khanna ,  Xin Kang ,  Ali Taha ,  James Tschanz ,  William Zand ,  Robert Kwasnick

IPC: G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/50

CPC classification number: G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/5094

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to optimize a guard band of a hardware resource. An example apparatus includes at least one storage device, and at least one processor to execute instructions to identify a phase of a workload based on an output from a machine-learning model, the phase based on a utilization of one or more hardware resources, and based on the phase, control a guard band of a first hardware resource of the one or more hardware resources.