公开(公告)号：US10755984B2

公开(公告)日：2020-08-25

申请号：US15576396

申请日：2015-06-24

Applicant: INTEL CORPORATION

Inventor： Glenn A. Glass ,  Ying Pang ,  Nabil G. Mistkawi ,  Anand S. Murthy ,  Tahir Ghani ,  Huang-Lin Chao

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/161 ,  H01L29/20 ,  H01L29/66

Abstract: Techniques are disclosed for customization of fin-based transistor devices to provide a diverse range of channel configurations and/or material systems, and within the same integrated circuit die. Sacrificial fins are removed via wet and/or dry etch chemistries configured to provide trench bottoms that are non-faceted and have no or otherwise low-ion damage. The trench is then filled with desired semiconductor material. A trench bottom having low-ion damage and non-faceted morphology encourages a defect-free or low defect interface between the substrate and the replacement material. In an embodiment, each of a first set of the sacrificial silicon fins is recessed and replaced with a p-type material, and each of a second set of the sacrificial fins is recessed and replaced with an n-type material. Another embodiment may include a combination of native fins (e.g., Si) and replacement fins (e.g., SiGe). Another embodiment may include replacement fins all of the same configuration.

公开(公告)号：US11476164B2

公开(公告)日：2022-10-18

申请号：US16631352

申请日：2017-09-26

Applicant: Intel Corporation

Inventor： Ying Pang ,  Florian Gstrein ,  Dan S. Lavric ,  Ashish Agrawal ,  Robert Niffenegger ,  Padmanava Sadhukhan ,  Robert W. Heussner ,  Joel M. Gregie

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/66

Abstract: Integrated circuit structures having differentiated workfunction layers are described. In an example, an integrated circuit structure includes a first gate electrode above a substrate. The first gate electrode includes a first workfunction material layer. A second gate electrode is above the substrate. The second gate electrode includes a second workfunction material layer different in composition from the first workfunction material layer. The second gate electrode does not include the first workfunction material layer, and the first gate electrode does not include the second workfunction material layer. A third gate electrode above is the substrate. The third gate electrode includes a third workfunction material layer different in composition from the first workfunction material layer and the second workfunction material layer. The third gate electrode does not include the first workfunction material layer and does not include the second workfunction material layer.

公开(公告)号：US10510848B2

公开(公告)日：2019-12-17

申请号：US15576150

申请日：2015-06-24

Applicant: INTEL CORPORATION

Inventor： Glenn A. Glass ,  Ying Pang ,  Anand S. Murthy ,  Tahir Ghani ,  Karthik Jambunathan

IPC: H01L29/40 ,  H01L21/8238 ,  H01L29/423 ,  H01L27/092 ,  H01L29/786 ,  H01L29/10 ,  H01L29/775 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16 ,  H01L29/20 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02

Abstract: Techniques are disclosed for reducing off-state leakage of fin-based transistors through the use of a sub-fin passivation layer. In some cases, the techniques include forming sacrificial fins in a bulk silicon substrate and depositing and planarizing shallow trench isolation (STI) material, removing and replacing the sacrificial silicon fins with a replacement material (e.g., SiGe or III-V material), removing at least a portion of the STI material to expose the sub-fin areas of the replacement fins, applying a passivating layer/treatment/agent to the exposed sub-fins, and re-depositing and planarizing additional STI material. Standard transistor forming processes can then be carried out to complete the transistor device. The techniques generally provide the ability to add arbitrary passivation layers for structures that are grown in STI-based trenches. The passivation layer inhibits sub-fin source-to-drain (and drain-to-source) current leakage.

公开(公告)号：US10147817B2

公开(公告)日：2018-12-04

申请号：US15860292

申请日：2018-01-02

Applicant: INTEL CORPORATION

Inventor： Glenn A. Glass ,  Anand S. Murthy ,  Tahir Ghani ,  Ying Pang ,  Nabil G. Mistkawi

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/167 ,  H01L21/8238 ,  B82Y10/00 ,  H01L29/775 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/165 ,  H01L21/02 ,  H01L21/306 ,  H01L21/762 ,  H01L27/092 ,  H01L29/45 ,  H01L29/423 ,  H01L29/786 ,  H01L29/161

Abstract: Techniques are disclosed for improved integration of germanium (Ge)-rich p-MOS source/drain contacts to, for example, reduce contact resistance. The techniques include depositing the p-type Ge-rich layer directly on a silicon (Si) surface in the contact trench location, because Si surfaces are favorable for deposition of high quality conductive Ge-rich materials. In one example method, the Ge-rich layer is deposited on a surface of the Si substrate in the source/drain contact trench locations, after removing a sacrificial silicon germanium (SiGe) layer previously deposited in the source/drain locations. In another example method, the Ge-rich layer is deposited on a Si cladding layer in the contact trench locations, where the Si cladding layer is deposited on a functional p-type SiGe layer. In some cases, the Ge-rich layer comprises at least 50% Ge (and may contain tin (Sn) and/or Si) and is boron (B) doped at levels above 1E20 cm−3.

公开(公告)号：US10541334B2

公开(公告)日：2020-01-21

申请号：US16199445

申请日：2018-11-26

Applicant: INTEL CORPORATION

Inventor： Glenn A. Glass ,  Anand S. Murthy ,  Tahir Ghani ,  Ying Pang ,  Nabil G. Mistkawi

IPC: H01L29/78 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/161 ,  H01L21/762 ,  H01L27/092 ,  H01L29/167 ,  H01L29/45 ,  H01L29/423 ,  H01L29/786 ,  B82Y10/00 ,  H01L29/775 ,  H01L29/06 ,  H01L29/417 ,  H01L29/165 ,  H01L21/02 ,  H01L21/306 ,  H01L29/08

Abstract: Techniques are disclosed for improved integration of germanium (Ge)-rich p-MOS source/drain contacts to, for example, reduce contact resistance. The techniques include depositing the p-type Ge-rich layer directly on a silicon (Si) surface in the contact trench location, because Si surfaces are favorable for deposition of high quality conductive Ge-rich materials. In one example method, the Ge-rich layer is deposited on a surface of the Si substrate in the source/drain contact trench locations, after removing a sacrificial silicon germanium (SiGe) layer previously deposited in the source/drain locations. In another example method, the Ge-rich layer is deposited on a Si cladding layer in the contact trench locations, where the Si cladding layer is deposited on a functional p-type SiGe layer. In some cases, the Ge-rich layer comprises at least 50% Ge (and may contain tin (Sn) and/or Si) and is boron (B) doped at levels above 1E20 cm−3.

公开(公告)号：US09859424B2

公开(公告)日：2018-01-02

申请号：US15116453

申请日：2014-03-21

Applicant: INTEL CORPORATION

Inventor： Glenn A. Glass ,  Anand S. Murthy ,  Tahir Ghani ,  Ying Pang ,  Nabil G. Mistkawi

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/167 ,  H01L21/8238 ,  B82Y10/00 ,  H01L29/775 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/165 ,  H01L21/02 ,  H01L21/306 ,  H01L21/762 ,  H01L27/092 ,  H01L29/45 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/7848 ,  B82Y10/00 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/41783 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/78 ,  H01L29/785 ,  H01L29/78696

Abstract: Techniques are disclosed for improved integration of germanium (Ge)-rich p-MOS source/drain contacts to, for example, reduce contact resistance. The techniques include depositing the p-type Ge-rich layer directly on a silicon (Si) surface in the contact trench location, because Si surfaces are favorable for deposition of high quality conductive Ge-rich materials. In one example method, the Ge-rich layer is deposited on a surface of the Si substrate in the source/drain contact trench locations, after removing a sacrificial silicon germanium (SiGe) layer previously deposited in the source/drain locations. In another example method, the Ge-rich layer is deposited on a Si cladding layer in the contact trench locations, where the Si cladding layer is deposited on a functional p-type SiGe layer. In some cases, the Ge-rich layer comprises at least 50% Ge (and may contain tin (Sn) and/or Si) and is boron (B) doped at levels above 1E20 cm−3.