公开(公告)号：US12113068B2

公开(公告)日：2024-10-08

申请号：US17031832

申请日：2020-09-24

申请人： Intel Corporation

发明人： Dan S. Lavric ,  Dax M. Crum ,  Omair Saadat ,  Oleg Golonzka ,  Tahir Ghani

IPC分类号： H01L27/092 ,  B82Y10/00 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC分类号： H01L27/0924 ,  H01L21/823821 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/775

摘要： Gate-all-around integrated circuit structures having additive metal gates are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires, and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, the first gate stack having a P-type conductive layer with a first portion surrounding the nanowires of the first vertical arrangement of horizontal nanowires and a second portion extending laterally beside and spaced apart from the first portion. A second gate stack is over the second vertical arrangement of horizontal nanowires, the second gate stack having an N-type conductive layer with a first portion surrounding the nanowires of the second vertical arrangement of horizontal nanowires and a second portion adjacent to and in contact with the second portion of the P-type conductive layer.

公开(公告)号：US20240006533A1

公开(公告)日：2024-01-04

申请号：US17856982

申请日：2022-07-02

申请人： Intel Corporation

发明人： Gilbert Dewey ,  Siddharth Chouksey ,  Nazila Haratipour ,  Christopher Jezewski ,  Jitendra Kumar Jha ,  Ilya V. Karpov ,  Matthew V. Metz ,  Arnab Sen Gupta ,  I-Cheng Tung ,  Nancy Zelick ,  Chi-Hing Choi ,  Dan S. Lavric

IPC分类号： H01L29/78 ,  H01L29/167

CPC分类号： H01L29/785 ,  H01L29/167

摘要： Contacts to p-type source/drain regions comprise a boride, indium, or gallium metal compound layer. The boride, indium, or gallium metal compound layers can aid in forming thermally stable low resistance contacts. A boride, indium, or gallium metal compound layer is positioned between the source/drain region and the contact metal layer. A boride, indium, or gallium metal compound layer can be used in contacts contacting p-type source/drain regions comprising boron, indium, or gallium as the primary dopant, respectively. The boride, indium, or gallium metal compound layers prevent diffusion of boron, indium, or gallium from the source/drain region into the metal contact layer and dopant deactivation in the source/drain region due to annealing and other high-temperature processing steps that occur after contact formation. Boride, indium, or gallium metal contact layers can also reduce the amount of silicide that forms in source/drain regions during processing by limiting contact metal diffusion into source/drain regions.

公开(公告)号：US11476164B2

公开(公告)日：2022-10-18

申请号：US16631352

申请日：2017-09-26

申请人： Intel Corporation

发明人： Ying Pang ,  Florian Gstrein ,  Dan S. Lavric ,  Ashish Agrawal ,  Robert Niffenegger ,  Padmanava Sadhukhan ,  Robert W. Heussner ,  Joel M. Gregie

IPC分类号： H01L27/092 ,  H01L21/8238 ,  H01L29/66

摘要： Integrated circuit structures having differentiated workfunction layers are described. In an example, an integrated circuit structure includes a first gate electrode above a substrate. The first gate electrode includes a first workfunction material layer. A second gate electrode is above the substrate. The second gate electrode includes a second workfunction material layer different in composition from the first workfunction material layer. The second gate electrode does not include the first workfunction material layer, and the first gate electrode does not include the second workfunction material layer. A third gate electrode above is the substrate. The third gate electrode includes a third workfunction material layer different in composition from the first workfunction material layer and the second workfunction material layer. The third gate electrode does not include the first workfunction material layer and does not include the second workfunction material layer.

公开(公告)号：US12046654B2

公开(公告)日：2024-07-23

申请号：US16912118

申请日：2020-06-25

申请人： Intel Corporation

发明人： Dan S. Lavric ,  Glenn A. Glass ,  Thomas T. Troeger ,  Suresh Vishwanath ,  Jitendra Kumar Jha ,  John F. Richards ,  Anand S. Murthy ,  Srijit Mukherjee

IPC分类号： H01L29/45 ,  H01L21/28 ,  H01L21/285 ,  H01L29/08 ,  H01L29/161 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/45 ,  H01L21/28088 ,  H01L21/28518 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/4966 ,  H01L29/66795 ,  H01L29/7851

摘要： Approaches for fabricating an integrated circuit structure including a titanium silicide material, and the resulting structures, are described. In an example, an integrated circuit structure includes a semiconductor fin above a substrate, a gate electrode over the top and adjacent to the sidewalls of a portion of the semiconductor fin. A titanium silicide material is in direct contact with each of first and second epitaxial semiconductor source or drain structures at first and second sides of the gate electrode. The titanium silicide material is conformal with and hermetically sealing a non-flat topography of each of the first and second epitaxial semiconductor source or drain structures. The titanium silicide material has a total atomic composition including 95% or greater stoichiometric TiSi2.

公开(公告)号：US20240321892A1

公开(公告)日：2024-09-26

申请号：US18125880

申请日：2023-03-24

申请人： Intel Corporation

发明人： Leonard P. Guler ,  Glenn Glass ,  Jessica Panella ,  Dan S. Lavric ,  Charles H. Wallace

IPC分类号： H01L27/12 ,  H01L21/84

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775

摘要： Techniques to form semiconductor devices having one or more epitaxial source or drain regions formed between dielectric walls that separate each adjacent pair of source or drain regions. In an example, a semiconductor device includes a semiconductor region extending in a first direction from a source or drain region. Dielectric walls extend in the first direction adjacent to opposite sides of the source or drain region. The first and second dielectric walls also extend in the first direction through a gate structure present over the semiconductor region. A dielectric liner exists between at least a portion of the first side of the source or drain region and the first dielectric wall and/or at least a portion of the second side of the source or drain region and the second dielectric wall. The dielectric walls may separate the source or drain region from other adjacent source or drain regions.

公开(公告)号：US20240186127A1

公开(公告)日：2024-06-06

申请号：US18399237

申请日：2023-12-28

申请人： Intel Corporation

发明人： Ilya V. Karpov ,  Aaron A. Budrevich ,  Gilbert Dewey ,  Matthew V. Metz ,  Jack T. Kavalieros ,  Dan S. Lavric

IPC分类号： H01J37/34 ,  C23C14/34 ,  H01L21/285 ,  H01L29/08 ,  H01L29/45

CPC分类号： H01J37/3426 ,  C23C14/3414 ,  H01L21/28518 ,  H01L21/28568 ,  H01L29/0847 ,  H01L29/45 ,  H01L29/456 ,  H01J2237/332

摘要： An integrated circuit structure includes a source or drain region, and a contact coupled to the source or drain region. Sputter targets that include metals doped with the appropriate dopant types are used to deposit a conductive layer on the source or drain region that is annealed to form a region including metals and semiconductor materials between the source or drain region and the contact. A first dopant is within the source or drain region, and a second dopant is within the region. In one example, the first dopant is elementally different from the second dopant. In another example, the first dopant is elementally the same as the second dopant, wherein a concentration of the first dopant within a section of the source or drain region is within 20% of a concentration of the second dopant within the region.

公开(公告)号：US20240006506A1

公开(公告)日：2024-01-04

申请号：US17856979

申请日：2022-07-02

申请人： Intel Corporation

发明人： Gilbert Dewey ,  Siddharth Chouksey ,  Nazila Haratipour ,  Christopher Jezewski ,  Jitendra Kumar Jha ,  Ilya V. Karpov ,  Jack T. Kavalieros ,  Arnab Sen Gupta ,  I-Cheng Tung ,  Nancy Zelick ,  Chi-Hing Choi ,  Dan S. Lavric

IPC分类号： H01L29/45 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/78 ,  H01L27/088

CPC分类号： H01L29/458 ,  H01L29/41733 ,  H01L29/41791 ,  H01L29/41775 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/7851 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/401

摘要： Contacts to n-type source/drain regions comprise a phosphide or arsenide metal compound layer. The phosphide or arsenide metal compound layers can aid in forming thermally stable low resistance contacts. A phosphide or arsenide metal compound layer is positioned between the source/drain region and the contact metal layer of the contact. A phosphide or arsenic metal compound layer can be used in contacts contacting n-type source/drain regions comprising phosphorous or arsenic as the primary dopant, respectively. The phosphide or arsenide metal compound layers prevent diffusion of phosphorous or arsenic from the source/drain region into the metal contact layer and dopant deactivation in the source/drain region due to annealing and other high-temperature processing steps that occur after contact formation. Phosphide and arsenide metal contact layers can also reduce the amount of silicide that forms in source/drain regions during processing by limiting the amount of contact metal that diffuses into source/drain regions.

公开(公告)号：US12051698B2

公开(公告)日：2024-07-30

申请号：US17030350

申请日：2020-09-23

申请人： Intel Corporation

发明人： Daniel G. Ouellette ,  Daniel B. O'Brien ,  Jeffrey S. Leib ,  Orb Acton ,  Lukas Baumgartel ,  Dan S. Lavric ,  Dax M. Crum ,  Oleg Golonzka ,  Tahir Ghani

IPC分类号： H01L27/00 ,  H01L27/092 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/775

CPC分类号： H01L27/0924 ,  H01L29/0673 ,  H01L29/408 ,  H01L29/42392 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/775

摘要： Gate-all-around integrated circuit structures having molybdenum nitride metal gates and gate dielectrics with a dipole layer are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires, and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, the first gate stack having a P-type conductive layer on a first gate dielectric. The P-type conductive layer includes molybdenum and nitrogen. A second gate stack is over the second vertical arrangement of horizontal nanowires, the second gate stack having an N-type conductive layer on a second gate dielectric.

公开(公告)号：US20240204103A1

公开(公告)日：2024-06-20

申请号：US18065657

申请日：2022-12-14

申请人： Intel Corporation

发明人： Rohit Galatage ,  Cheng-Ying Huang ,  Dan S. Lavric ,  Sarah Atanasov ,  Shao Ming Koh ,  Jack T. Kavalieros ,  Marko Radosavljevic ,  Mauro J. Kobrinsky ,  Jami Wiedemer ,  Munzarin Qayyum ,  Evan Clinton

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49

CPC分类号： H01L29/785 ,  H01L29/0669 ,  H01L29/42392 ,  H01L29/49 ,  H01L2029/7858

摘要： Disclosed herein are transistor gate-channel arrangements with transistor gate stacks that include multiple dipole materials, and related methods and devices. For example, in some embodiments, a transistor gate-channel arrangement may include a channel material and a transistor gate stack. The transistor gate stack may include a gate electrode material and a gate dielectric material between the gate electrode material and the channel material, where the gate dielectric material includes a first dipole material and a second dipole material where one of the first and second dipole materials is a P-shifter dipole material and the other one is an N-shifter dipole material.

公开(公告)号：US11984506B2

公开(公告)日：2024-05-14

申请号：US16912103

申请日：2020-06-25

申请人： Intel Corporation

发明人： Vishal Tiwari ,  Rishabh Mehandru ,  Dan S. Lavric ,  Michal Mleczko ,  Szuya S. Liao

IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L29/40 ,  H01L29/51 ,  H01L29/06

CPC分类号： H01L29/7843 ,  H01L21/28176 ,  H01L29/401 ,  H01L29/513 ,  H01L29/517 ,  H01L29/0653

摘要： Field effect transistors having field effect transistors having gate dielectrics with dipole layers and having gate stressor layers, and methods of fabricating field effect transistors having gate dielectrics with dipole layers and having gate stressor layers, are described. In an example, an integrated circuit structure includes a semiconductor channel structure including a monocrystalline material. A gate dielectric is over the semiconductor channel structure, the gate dielectric including a high-k dielectric layer on a dipole material layer, and the dipole material layer distinct from the high-k dielectric layer. A gate electrode has a workfunction layer on the high-k dielectric layer, the workfunction layer including a metal. A first source or drain structure is at a first side of the gate electrode. A second source or drain structure is at a second side of the gate electrode opposite the first side.