公开(公告)号：US20160041945A1

公开(公告)日：2016-02-11

申请号：US14453341

申请日：2014-08-06

Applicant: Intel Corporation

Inventor： Michael Mishaeli ,  Stanislav Shwartsman ,  Gal Ofir ,  Yulia Kurolap

IPC: G06F15/78 ,  G06F1/32 ,  G06F9/30

CPC classification number: G06F1/3287 ,  G06F1/32 ,  G06F9/30145 ,  G06F15/7807 ,  Y02D10/171 ,  Y02D50/20

Abstract: A processor includes a core with locally-gated circuitry, a decode unit, a local power gate (LPG) coupled to the locally-gated circuitry, and an execution unit. The decode unit includes logic to decode a store broadcast instruction of a specified width. The LPG includes logic to selectively provide power to the locally-gated circuitry, activate power to a first portion of the locally-gated circuitry for execution of full cache-line memory operations, and deactivate power to a second portion of the locally-gated circuitry the locally-gated circuitry. The execution unit includes logic to execute, by the first portion of the locally-gated circuitry for execution of full cache-line memory operations, the store broadcast instruction, the store broadcast instruction to store data of the specified width to storage of the processor.

Abstract translation: 处理器包括具有本地门控电路的核心，解码单元，耦合到本地门控电路的本地电源门（LPG）以及执行单元。 解码单元包括用于解码指定宽度的存储广播指令的逻辑。 LPG包括用于选择性地向本地门控电路提供电力的逻辑，激活本地门控电路的第一部分以执行完全高速缓存行存储器操作的功率，以及去激活局部门控电路的第二部分的功率 本地门控电路。 执行单元包括由用于执行全高速缓存行存储器操作的本地门控电路的第一部分执行存储广播指令，存储广播指令以存储指定宽度的数据以存储处理器的逻辑。

公开(公告)号：US09501132B2

公开(公告)日：2016-11-22

申请号：US14453341

申请日：2014-08-06

Applicant: Intel Corporation

Inventor： Michael Mishaeli ,  Stanislav Shwartsman ,  Gal Ofir ,  Yulia Kurolap

IPC: G06F1/32 ,  G06F9/30 ,  G06F15/78

CPC classification number: G06F1/3287 ,  G06F1/32 ,  G06F9/30145 ,  G06F15/7807 ,  Y02D10/171 ,  Y02D50/20

Abstract: A processor includes a core with locally-gated circuitry, a decode unit, a local power gate (LPG) coupled to the locally-gated circuitry, and an execution unit. The decode unit includes logic to decode a store broadcast instruction of a specified width. The LPG includes logic to selectively provide power to the locally-gated circuitry, activate power to a first portion of the locally-gated circuitry for execution of full cache-line memory operations, and deactivate power to a second portion of the locally-gated circuitry the locally-gated circuitry. The execution unit includes logic to execute, by the first portion of the locally-gated circuitry for execution of full cache-line memory operations, the store broadcast instruction, the store broadcast instruction to store data of the specified width to storage of the processor.

Abstract translation: 处理器包括具有本地门控电路的核心，解码单元，耦合到本地门控电路的本地电源门（LPG）以及执行单元。 解码单元包括用于解码指定宽度的存储广播指令的逻辑。 LPG包括用于选择性地向本地门控电路提供电力的逻辑，激活本地门控电路的第一部分以执行完全高速缓存行存储器操作的功率，以及去激活局部门控电路的第二部分的功率 本地门控电路。 执行单元包括由用于执行全高速缓存行存储器操作的本地门控电路的第一部分执行存储广播指令，存储广播指令以存储指定宽度的数据以存储处理器的逻辑。

公开(公告)号：US08935514B2

公开(公告)日：2015-01-13

申请号：US14012344

申请日：2013-08-28

Applicant: Intel Corporation

Inventor： Ohad Falik ,  Lihu Rappoport ,  Ron Gabor ,  Yulia Kurolap ,  Michael Mishaeli

IPC: G06F9/40 ,  G06F9/30 ,  G06F9/32 ,  G06F9/38

CPC classification number: G06F9/30145 ,  G06F9/30032 ,  G06F9/30043 ,  G06F9/3017 ,  G06F9/30181 ,  G06F9/325 ,  G06F9/3855 ,  G06F9/3857

Abstract: In one embodiment, the present invention includes an instruction decoder that can receive an incoming instruction and a path select signal and decode the incoming instruction into a first instruction code or a second instruction code responsive to the path select signal. The two different instruction codes, both representing the same incoming instruction may be used by an execution unit to perform an operation optimized for different data lengths. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括一个指令解码器，其可以接收输入指令和路径选择信号，并且响应于路径选择信号将输入指令解码为第一指令代码或第二指令代码。 代表相同输入指令的两个不同的指令代码可以被执行单元用于执行针对不同数据长度优化的操作。 描述和要求保护其他实施例。