公开(公告)号：US09544002B2

公开(公告)日：2017-01-10

申请号：US14156674

申请日：2014-01-16

Applicant: Intel IP Corporation

Inventor： Benjamin Jann ,  Hasnain Lakdawala

IPC: H04M1/00 ,  H04B1/3827 ,  H04W88/02 ,  H04W52/02

CPC classification number: H04B1/3833 ,  H04W52/0274 ,  H04W88/02 ,  Y02D70/00 ,  Y02D70/1222 ,  Y02D70/1224 ,  Y02D70/1242 ,  Y02D70/1262 ,  Y02D70/1264 ,  Y02D70/142 ,  Y02D70/144 ,  Y02D70/146

Abstract: The disclosure is directed to a circuit arrangement and method that provide efficient concurrent transmit and receive, transmit only and receive only of wireless signals. In one implementation, a circuit arrangement is provided that incorporates uses a single antenna to achieve concurrent transmit and receive, transmit only and receive only of wireless signals. A dual amplifier structure may be provided, and at least one of the amplifiers associated with the dual amplifier structure is amplitude tunable in order to ensure that each amplifier of the dual amplifier structure provides substantially the same or the same signal amplification. Unwanted transmit signals detected by a receiving circuit arrangement may be used to cause a processor to generate a digital code word that is used to modify a signal amplification provided by at least one of the amplifiers associated with the dual amplifier structure.

Abstract translation: 本公开涉及一种电路装置和方法，其提供有效的并发发送和接收，仅发送和仅接收无线信号。 在一个实施方案中，提供了一种电路装置，其结合使用单个天线来实现并发的发送和接收，仅发送和仅接收无线信号。 可以提供双放大器结构，并且与双放大器结构相关联的放大器中的至少一个是幅度可调的，以便确保双放大器结构的每个放大器提供基本上相同或相同的信号放大。 可以使用由接收电路装置检测到的不需要的发送信号来使处理器产生用于修改由与双放大器结构相关联的至少一个放大器提供的信号放大的数字码字。

公开(公告)号：US20190305732A1

公开(公告)日：2019-10-03

申请号：US15937906

申请日：2018-03-28

Applicant: Intel IP Corporation

Inventor： Benjamin Jann

IPC: H03F1/30 ,  H03G1/00 ,  H03F1/22 ,  H03D7/12 ,  H03D9/06 ,  H03H19/00

Abstract: A circuit containing a first cascode circuit and a second cascode circuit is proposed. The first circuit and the second cascode circuit are stacked between two power supply terminals. An output signal terminal of the circuit is coupled to a node connecting the first cascode circuit and the second cascode circuit. A first signal path is provided between the first cascode circuit and a common ground terminal and a second signal path is provided between the second cascode circuit and the common ground terminal.

公开(公告)号：US20190305402A1

公开(公告)日：2019-10-03

申请号：US15939806

申请日：2018-03-29

Applicant: Intel IP Corporation

Inventor： Sidharth Dalmia ,  Jonathan Jensen ,  Ozgur Inac ,  Trang Thai ,  William James Lambert ,  Benjamin Jann

IPC: H01Q1/24 ,  H01Q9/04 ,  H01Q1/22

Abstract: Disclosed herein are integrated circuit (IC) packages, antenna boards, antenna modules, and communication devices (e.g., for millimeter wave communications). For example, in some embodiments, an antenna module may include: a logic die; a radio frequency front-end (RFFE) die in electrical communication with the logic die; and an antenna patch, wherein the RFFE die is closer to the antenna patch than the logic die is to the antenna patch.

公开(公告)号：US11380979B2

公开(公告)日：2022-07-05

申请号：US15939806

申请日：2018-03-29

Applicant: Intel IP Corporation

Inventor： Sidharth Dalmia ,  Jonathan Jensen ,  Ozgur Inac ,  Trang Thai ,  William James Lambert ,  Benjamin Jann

IPC: H01Q1/24 ,  H01Q9/04 ,  H01Q1/22 ,  H01Q1/38 ,  H01L23/66

Abstract: Disclosed herein are integrated circuit (IC) packages, antenna boards, antenna modules, and communication devices (e.g., for millimeter wave communications). For example, in some embodiments, an antenna module may include: a logic die; a radio frequency front-end (RFFE) die in electrical communication with the logic die; and an antenna patch, wherein the RFFE die is closer to the antenna patch than the logic die is to the antenna patch.

公开(公告)号：US10536118B2

公开(公告)日：2020-01-14

申请号：US15937906

申请日：2018-03-28

Applicant: Intel IP Corporation

Inventor： Benjamin Jann

IPC: H03F3/04 ,  H03F1/30 ,  H03G1/00 ,  H03F1/22 ,  H03H19/00 ,  H03D7/12 ,  H03D9/06

Abstract: A circuit containing a first cascode circuit and a second cascode circuit is proposed. The first circuit and the second cascode circuit are stacked between two power supply terminals. An output signal terminal of the circuit is coupled to a node connecting the first cascode circuit and the second cascode circuit. A first signal path is provided between the first cascode circuit and a common ground terminal and a second signal path is provided between the second cascode circuit and the common ground terminal.