公开(公告)号：US20180165240A1

公开(公告)日：2018-06-14

申请号：US15373033

申请日：2016-12-08

申请人： INTEL IP CORPORATION

发明人： Helmut Reinig ,  Todor M. Mladenov ,  Simona Bernardi ,  Robert De Gruijl

IPC分类号： G06F13/40 ,  G06F13/16 ,  G06F13/42

CPC分类号： G06F13/4022 ,  G06F13/1642 ,  G06F13/1673 ,  G06F13/4282

摘要： A network interface is provided which comprises: a first buffer configured to buffer a first flow of a first type of commands from a first device to a second device, wherein the first device is configured in accordance with a first bus interconnect protocol and the second device is configured in accordance with a second bus interconnect protocol; a second buffer configured to buffer a second flow of a second type of commands from the first device to the second device; and an arbiter configured to arbitrate between the first flow and the second flow, and selectively output one or more commands of the first type and one or more commands of the second type.

公开(公告)号：US20180375602A1

公开(公告)日：2018-12-27

申请号：US15630368

申请日：2017-06-22

申请人： Intel IP Corporation

发明人： Todor M. Mladenov ,  Helmut Reinig ,  Simona Bernardi

IPC分类号： H04J3/00 ,  H04L12/933 ,  H04L12/863

摘要： Embodiments of the present disclosure may relate to an apparatus with a first component and a second component coupled with the first component by a plurality of signal wires. A first wire of the plurality of signal wires may be to carry a command byte of a packet and a first data byte of the packet from the first component to the second component. A second wire of the plurality of signal wires may be to carry a second data byte of the packet from the first component to the second component when the first signal wire carries the command byte of the packet and carry a third data byte of the packet from the first component to the second component when the first signal wire carries the first data byte of the packet. Other embodiments may be described or claimed.

公开(公告)号：US11171856B2

公开(公告)日：2021-11-09

申请号：US15835393

申请日：2017-12-07

申请人： Intel IP Corporation

发明人： Pradeep Kumar ,  Amit Badole ,  Arumugam Vijayaraman ,  Helmut Reinig ,  Patrik Eder ,  Vladimir Todorov ,  Abhiram Anantharamu

IPC分类号： H04L12/26 ,  H04J3/06 ,  G06F1/04 ,  H04L12/841 ,  G06F1/14

摘要： An apparatus is provided which comprises: a first network interface (NI) to receive data from a source; a second NI coupled to a target; and a circuitry to generate a sequence of source timestamps and a sequence of target timestamps, wherein the first NI is to receive the sequence of source timestamps, and associate a first source timestamp of the sequence of source timestamps with the data, and wherein the second NI is to receive: the data with the first source timestamp from the first NI and the sequence of target timestamps from the circuitry, the second NI to generate a timestamp for the data, based at least in part on the first source timestamp and a first target timestamp of the sequence of target timestamps.

公开(公告)号：US20190036803A1

公开(公告)日：2019-01-31

申请号：US15835393

申请日：2017-12-07

申请人： Intel IP Corporation

发明人： Pradeep Kumar ,  Amit Badole ,  Arumugam Vijayaraman ,  Helmut Reinig ,  Patrik Eder ,  Vladimir Todorov ,  Abhiram Anantharamu

IPC分类号： H04L12/26 ,  H04J3/06 ,  G06F1/04

摘要： An apparatus is provided which comprises: a first network interface (NI) to receive data from a source; a second NI coupled to a target; and a circuitry to generate a sequence of source timestamps and a sequence of target timestamps, wherein the first NI is to receive the sequence of source timestamps, and associate a first source timestamp of the sequence of source timestamps with the data, and wherein the second NI is to receive: the data with the first source timestamp from the first NI and the sequence of target timestamps from the circuitry, the second NI to generate a timestamp for the data, based at least in part on the first source timestamp and a first target timestamp of the sequence of target timestamps.