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    VARIABLE PIN FIN CONSTRUCTION TO FACILITATE COMPLIANT COLD PLATES
    1.
    发明申请
    VARIABLE PIN FIN CONSTRUCTION TO FACILITATE COMPLIANT COLD PLATES 审中-公开

    公开(公告)号：US20200091032A1

    公开(公告)日：2020-03-19

    申请号：US16676515

    申请日：2019-11-07

    申请人： International Business Machines Corporation

    发明人： Mark Delorman Schultz

    IPC分类号： H01L23/367 ,  H01L21/48

    摘要： A device can comprise a plurality of layers stacked and bonded on one another, wherein at least one layer of the plurality of layers comprises: a first active region comprising first pin portions positioned in a first planar arrangement; and a second active region comprising second pin portions positioned in a second planar arrangement, wherein the second planar arrangement is different from the first planar arrangement. The device can also comprise a conformable layer adjacent to at least one of the plurality of layers.

    Wafer level integration for embedded cooling
    2.
    发明授权
    Wafer level integration for embedded cooling 有权

    公开(公告)号：US10170392B2

    公开(公告)日：2019-01-01

    申请号：US15479810

    申请日：2017-04-05

    申请人： International Business Machines Corporation

    发明人： Timothy Joseph Chainer ,  Pritish Ranjan Parida ,  Mark Delorman Schultz

    IPC分类号： H01L23/42 ,  H01L23/46 ,  H01L25/00 ,  H01L23/427 ,  H01L21/82 ,  H01L25/065

    摘要： Techniques for wafer level integration of embedded cooling structures for integrated circuit devices are provided. In one embodiment, a method includes forming channel structures on a first surface of a silicon first wafer, wherein the channel structures respectively include radial channels that extend from central fluid distribution areas, and wherein integrated circuits are formed on a second surface of the silicon first wafer that opposes the first surface. The method can further include bonding a manifold wafer to the first surface of the silicon wafer such that inlet openings formed through the manifold wafer respectively connect to the central fluid distribution areas, thereby enclosing the radial channels and forming a bonded structure.

    SYSTEM LEVEL MODEL FOR PUMPED TWO-PHASE COOLING SYSTEMS
    6.
    发明申请
    SYSTEM LEVEL MODEL FOR PUMPED TWO-PHASE COOLING SYSTEMS 审中-公开

    公开(公告)号：US20200166975A1

    公开(公告)日：2020-05-28

    申请号：US16775885

    申请日：2020-01-29

    申请人： International Business Machines Corporation

    发明人： Timothy Joseph Chainer ,  Leitao Chen ,  Pritish Ranjan Parida ,  Mark Delorman Schultz ,  Fanghao Yang

    IPC分类号： G06F1/20

    摘要： Techniques are provided for system level modeling of two-phase cooling systems. In one example, a computer-implemented method comprises determining, by a system operatively coupled to a processor, respective sets of steady state values for parameters at inlet-outlet junctions using a system model, wherein the determining is based on first user input specifying a cooling system design comprising a plurality of part objects, wherein adjacent part objects in a flow direction are connected at the inlet-outlet junctions. The computer-implemented method can also comprise generating, by the system, a graphical display that depicts the respective sets of parameter values at the inlet-outlet junctions.

    WAFER LEVEL INTEGRATION FOR EMBEDDED COOLING
    8.
    发明申请
    WAFER LEVEL INTEGRATION FOR EMBEDDED COOLING 审中-公开

    公开(公告)号：US20180294206A1

    公开(公告)日：2018-10-11

    申请号：US15849787

    申请日：2017-12-21

    申请人： International Business Machines Corporation

    发明人： Timothy Joseph Chainer ,  Pritish Ranjan Parida ,  Mark Delorman Schultz

    IPC分类号： H01L23/427 ,  H01L25/00 ,  H01L21/82 ,  H01L25/065

    摘要： Techniques for wafer level integration of embedded cooling structures for integrated circuit devices are provided. In one embodiment, a method includes forming channel structures on a first surface of a silicon first wafer, wherein the channel structures respectively comprise radial channels that extend from central fluid distribution areas, and wherein integrated circuits are formed on a second surface of the silicon first wafer that opposes the first surface. The method can further include bonding a manifold wafer to the first surface of the silicon wafer such that inlet openings formed through the manifold wafer respectively connect to the central fluid distribution areas, thereby enclosing the radial channels and forming a bonded structure.