摘要:
Responsive to selecting a particular queue from among at least two queues to place an incoming event into within a particular entry from among multiple entries ordered upon arrival of the particular queue each comprising a separate collision vector, a memory address for the incoming event is compared with each queued memory address for each queued event in the other entries in the at least one other queue. Responsive to the memory address for the incoming event matching at least one particular queued memory address for at least one particular queued event in the at least one other queue, at least one particular bit is set in a particular collision vector for the particular entry in at least one bit position from among the bits corresponding with at least one row entry position of the at least one particular queued memory address within the other entries.
摘要:
Responsive to selecting a particular queue from among at least two queues to place an incoming event into within a particular entry from among multiple entries ordered upon arrival of the particular queue each comprising a separate collision vector, a memory address for the incoming event is compared with each queued memory address for each queued event in the other entries in the at least one other queue. Responsive to the memory address for the incoming event matching at least one particular queued memory address for at least one particular queued event in the at least one other queue, at least one particular bit is set in a particular collision vector for the particular entry in at least one bit position from among the bits corresponding with at least one row entry position of the at least one particular queued memory address within the other entries.
摘要:
An order controller calculates an absolute value of a difference between a first counter value stored with a first next entry set to an active status in a first queue from among at least two queues and a second counter value stored with a second next entry set to the active status in a second queue. The order controller compares the absolute value with a counter midpoint value. The order controller, responsive to the absolute value being less than the counter midpoint value, selects a smaller value of the first counter value of the first counter value and the second counter value as a next event to process. The order controller, responsive to the absolute value being greater than or equal to the counter midpoint value, selects a larger value of the first counter value and the second counter value as the next event to process.
摘要:
An order controller stores each received event in a separate entry in one of at least two queues with a separate counter value set from an arrival order counter at the time of storage, wherein the arrival order counter is incremented after storage of each of the received events and on overflow the arrival order counter wraps back to zero. The order controller calculates an absolute value of the difference between a first counter value stored with an active first next entry in a first queue from among the at least two queues and a second counter value stored with an active second next entry in a second queue from among the at least two queues. The order controller compares the absolute value with a counter midpoint value to determine whether the first counter value was stored before the second counter value.
摘要:
Responsive to selecting a particular queue from among at least two queues to place an incoming event into within a particular entry from among multiple entries ordered upon arrival of the particular queue each comprising a separate collision vector, a memory address for the incoming event is compared with each queued memory address for each queued event in the other entries in the at least one other queue. Responsive to the memory address for the incoming event matching at least one particular queued memory address for at least one particular queued event in the at least one other queue, at least one particular bit is set in a particular collision vector for the particular entry in at least one bit position from among the bits corresponding with at least one row entry position of the at least one particular queued memory address within the other entries.
摘要:
Responsive to selecting a particular queue from among at least two queues to place an incoming event into within a particular entry from among multiple entries ordered upon arrival of the particular queue each comprising a separate collision vector, a memory address for the incoming event is compared with each queued memory address for each queued event in the other entries in the at least one other queue. Responsive to the memory address for the incoming event matching at least one particular queued memory address for at least one particular queued event in the at least one other queue, at least one particular bit is set in a particular collision vector for the particular entry in at least one bit position from among the bits corresponding with at least one row entry position of the at least one particular queued memory address within the other entries.
摘要:
Responsive to selecting a particular queue from among at least two queues to place an incoming event into within a particular entry from among multiple entries ordered upon arrival of the particular queue each comprising a separate collision vector, a memory address for the incoming event is compared with each queued memory address for each queued event in the other entries in the at least one other queue. Responsive to the memory address for the incoming event matching at least one particular queued memory address for at least one particular queued event in the at least one other queue, at least one particular bit is set in a particular collision vector for the particular entry in at least one bit position from among the bits corresponding with at least one row entry position of the at least one particular queued memory address within the other entries.
摘要:
An order controller calculates an absolute value of a difference between a first counter value stored with a first next entry set to an active status in a first queue from among at least two queues and a second counter value stored with a second next entry set to the active status in a second queue. The order controller compares the absolute value with a counter midpoint value. The order controller, responsive to the absolute value being less than the counter midpoint value, selects a smaller value of the first counter value of the first counter value and the second counter value as a next event to process. The order controller, responsive to the absolute value being greater than or equal to the counter midpoint value, selects a larger value of the first counter value and the second counter value as the next event to process.
摘要:
An order controller stores each received event in a separate entry in one of at least two queues with a separate counter value set from an arrival order counter at the time of storage, wherein the arrival order counter is incremented after storage of each of the received events and on overflow the arrival order counter wraps back to zero. The order controller calculates an absolute value of the difference between a first counter value stored with an active first next entry in a first queue from among the at least two queues and a second counter value stored with an active second next entry in a second queue from among the at least two queues. The order controller compares the absolute value with a counter midpoint value to determine whether the first counter value was stored before the second counter value.
摘要:
Responsive to selecting a particular queue from among at least two queues to place an incoming event into within a particular entry from among multiple entries ordered upon arrival of the particular queue each comprising a separate collision vector, a memory address for the incoming event is compared with each queued memory address for each queued event in the other entries in the at least one other queue. Responsive to the memory address for the incoming event matching at least one particular queued memory address for at least one particular queued event in the at least one other queue, at least one particular bit is set in a particular collision vector for the particular entry in at least one bit position from among the bits corresponding with at least one row entry position of the at least one particular queued memory address within the other entries.