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    MANAGING OUT-OF-ORDER MEMORY COMMAND EXECUTION FROM MULTIPLE QUEUES WHILE MAINTAINING DATA COHERENCY
    1.
    发明申请
    MANAGING OUT-OF-ORDER MEMORY COMMAND EXECUTION FROM MULTIPLE QUEUES WHILE MAINTAINING DATA COHERENCY 有权
    在维护数据相关性的同时，管理多个存储器的内存命令执行

    公开(公告)号：US20150212941A1

    公开(公告)日：2015-07-30

    申请号：US14680182

    申请日：2015-04-07

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Robert M. Dinkjian ,  Robert S. Horton ,  Michael Y. Lee ,  Bill N. On

    IPC分类号： G06F12/08 ,  G06F12/12

    CPC分类号： G06F12/0831 ,  G06F3/0653 ,  G06F12/00 ,  G06F12/0815 ,  G06F12/0877 ,  G06F12/128 ,  G06F13/1631 ,  G06F2212/603 ,  G06F2212/621

    摘要： Responsive to selecting a particular queue from among at least two queues to place an incoming event into within a particular entry from among multiple entries ordered upon arrival of the particular queue each comprising a separate collision vector, a memory address for the incoming event is compared with each queued memory address for each queued event in the other entries in the at least one other queue. Responsive to the memory address for the incoming event matching at least one particular queued memory address for at least one particular queued event in the at least one other queue, at least one particular bit is set in a particular collision vector for the particular entry in at least one bit position from among the bits corresponding with at least one row entry position of the at least one particular queued memory address within the other entries.

    摘要翻译： 响应于从至少两个队列中选择特定队列以将入局事件从特定队列到达的多个条目中的特定条目中放入每个包括单独的冲突向量的特定队列中，将进入事件的存储器地址与 在至少一个其他队列中的其他条目中的每个排队的事件的每个排队的存储器地址。 响应于对于至少一个其他队列中的至少一个特定排队事件的至少一个特定排队存储器地址的输入事件的存储器地址，至少一个特定位被设置在用于特定条目的特定冲突向量中 在对应于其他条目中的至少一个特定排队存储器地址的至少一个行入口位置的位中的至少一个位位置。

    Distributing multiplexing logic to remove multiplexor latency on the output path for variable clock cycle, delayed signals
    6.
    发明授权
    Distributing multiplexing logic to remove multiplexor latency on the output path for variable clock cycle, delayed signals 有权
    分配多路复用逻辑，以消除可变时钟周期，延迟信号的输出路径上的多路复用器延迟

    公开(公告)号：US08994424B2

    公开(公告)日：2015-03-31

    申请号：US13797252

    申请日：2013-03-12

    申请人： International Business Machines Corporation

    发明人： Huu N. Dinh ,  Robert S. Horton ,  Bill N. On

    IPC分类号： H03L7/00 ,  H03K5/159

    CPC分类号： H03K5/159 ,  H03K3/037 ,  H03K19/1737 ,  H03K2005/00104 ,  H03K2005/00241

    摘要： A logic unit is configured with least one multiplexor distributed along a delay path of a logic unit, wherein each at least one multiplexor is configured to receive two inputs and output one of the two inputs, wherein each at least one multiplexor is configured to select one of the two inputs to control a particular programmable number of clock cycles of delay added to a signal from 1 to N clock cycles. The logic unit is configured with at least two latches distributed along the delay path of the logic unit, wherein each at least one latch is configured to add a clock cycle of delay, wherein a terminating latch from among the at least two latches is configured to output the signal delayed by the particular programmable number of clock cycles.

    摘要翻译： 逻辑单元配置有沿着逻辑单元的延迟路径分布的至少一个多路复用器，其中每个至少一个复用器被配置为接收两个输入并输出两个输入中的一个，其中每个至少一个多路复用器被配置为选择一个 的两个输入来控制特定的可编程数量的延迟的时钟周期，这些时钟周期被添加到从1到N个时钟周期的信号。 逻辑单元配置有沿着逻辑单元的延迟路径分布的至少两个锁存器，其中每个至少一个锁存器被配置为增加延迟的时钟周期，其中来自所述至少两个锁存器的终止锁存器被配置为 输出延迟特定可编程时钟周期数的信号。

    MANAGING OUT-OF-ORDER MEMORY COMMAND EXECUTION FROM MULTIPLE QUEUES WHILE MAINTAINING DATA COHERENCY
    7.
    发明申请
    MANAGING OUT-OF-ORDER MEMORY COMMAND EXECUTION FROM MULTIPLE QUEUES WHILE MAINTAINING DATA COHERENCY 有权
    在维护数据相关性的同时，管理多个存储器的内存命令执行

    公开(公告)号：US20140223111A1

    公开(公告)日：2014-08-07

    申请号：US13757397

    申请日：2013-02-01

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Robert M. Dinkjian ,  Robert S. Horton ,  Michael Y. Lee ,  Bill N. On

    IPC分类号： G06F3/06

    CPC分类号： G06F12/0831 ,  G06F3/0653 ,  G06F12/00 ,  G06F12/0815 ,  G06F12/0877 ,  G06F12/128 ,  G06F13/1631 ,  G06F2212/603 ,  G06F2212/621

    摘要： Responsive to selecting a particular queue from among at least two queues to place an incoming event into within a particular entry from among multiple entries ordered upon arrival of the particular queue each comprising a separate collision vector, a memory address for the incoming event is compared with each queued memory address for each queued event in the other entries in the at least one other queue. Responsive to the memory address for the incoming event matching at least one particular queued memory address for at least one particular queued event in the at least one other queue, at least one particular bit is set in a particular collision vector for the particular entry in at least one bit position from among the bits corresponding with at least one row entry position of the at least one particular queued memory address within the other entries.

    摘要翻译： 响应于从至少两个队列中选择特定队列以将入局事件从特定队列到达的多个条目中的特定条目中放入每个包括单独的冲突向量的特定队列中，将进入事件的存储器地址与 在至少一个其他队列中的其他条目中的每个排队的事件的每个排队的存储器地址。 响应于对于至少一个其他队列中的至少一个特定排队事件的至少一个特定排队存储器地址的输入事件的存储器地址，至少一个特定位被设置在用于特定条目的特定冲突向量中 在对应于其他条目中的至少一个特定排队存储器地址的至少一个行入口位置的位中的至少一个位位置。

    Distributing multiplexing logic to remove multiplexor latency on the output path for variable clock cycle, delayed signals
    8.
    发明授权
    Distributing multiplexing logic to remove multiplexor latency on the output path for variable clock cycle, delayed signals 有权
    分配多路复用逻辑，以消除可变时钟周期，延迟信号的输出路径上的多路复用器延迟

    公开(公告)号：US09319040B2

    公开(公告)日：2016-04-19

    申请号：US14580655

    申请日：2014-12-23

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Huu N. Dinh ,  Robert S. Horton ,  Bill N. On

    IPC分类号： H03L7/00 ,  H03K5/159 ,  H03K3/037 ,  H03K19/173 ,  H03K5/00

    CPC分类号： H03K5/159 ,  H03K3/037 ,  H03K19/1737 ,  H03K2005/00104 ,  H03K2005/00241

    摘要： A controller sets a selector register of programmable delay signal logic is to a value equal to a required number of clock cycles of delay for signals output from an integrated circuit to an external memory. The controller controls a selection of additional logic along the output path to perform on the delayed signal within a clock cycle without any latency added to the output path by delay signal logic outputting the delayed signal. The controller waits required number of clock cycles after setting the selector register before using the delayed signal output by the delay signal logic onto an output path.

    摘要翻译： 控制器将可编程延迟信号逻辑的选择器寄存器设置为等于从集成电路输出到外部存储器的信号所需的延迟时钟周期数。 控制器控制沿着输出路径的附加逻辑的选择，以在时钟周期内执行延迟信号，而不会通过输出延迟信号的延迟信号逻辑将任何延迟加到输出路径上。 在使用由延迟信号逻辑输出的延迟信号到输出路径之后，控制器在设置选择器寄存器之后等待所需的时钟周期数。

    Managing out-of-order memory command execution from multiple queues while maintaining data coherency
    10.
    发明授权
    Managing out-of-order memory command execution from multiple queues while maintaining data coherency 有权
    在保持数据一致性的同时，从多个队列管理无序内存命令执行

    公开(公告)号：US09164908B2

    公开(公告)日：2015-10-20

    申请号：US14680182

    申请日：2015-04-07

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Robert M. Dinkjian ,  Robert S. Horton ,  Michael Y. Lee ,  Bill N. On

    IPC分类号： G06F12/00 ,  G06F12/08 ,  G06F12/12

    CPC分类号： G06F12/0831 ,  G06F3/0653 ,  G06F12/00 ,  G06F12/0815 ,  G06F12/0877 ,  G06F12/128 ,  G06F13/1631 ,  G06F2212/603 ,  G06F2212/621

    摘要： Responsive to selecting a particular queue from among at least two queues to place an incoming event into within a particular entry from among multiple entries ordered upon arrival of the particular queue each comprising a separate collision vector, a memory address for the incoming event is compared with each queued memory address for each queued event in the other entries in the at least one other queue. Responsive to the memory address for the incoming event matching at least one particular queued memory address for at least one particular queued event in the at least one other queue, at least one particular bit is set in a particular collision vector for the particular entry in at least one bit position from among the bits corresponding with at least one row entry position of the at least one particular queued memory address within the other entries.

    摘要翻译： 响应于从至少两个队列中选择特定队列以将入局事件从特定队列到达的多个条目中的特定条目中放入每个包括单独的冲突向量的特定队列中，将进入事件的存储器地址与 在至少一个其他队列中的其他条目中的每个排队的事件的每个排队的存储器地址。 响应于对于至少一个其他队列中的至少一个特定排队事件的至少一个特定排队存储器地址的输入事件的存储器地址，至少一个特定位被设置在用于特定条目的特定冲突向量中 在对应于其他条目中的至少一个特定排队存储器地址的至少一个行入口位置的位中的至少一个位位置。