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公开(公告)号:US20230170266A1
公开(公告)日:2023-06-01
申请号:US17536228
申请日:2021-11-29
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor: Ashim Dutta , Ruturaj Nandkumar Pujari , Saumya Sharma , Chih-Chao Yang
IPC: H01L21/66 , H01L23/544 , G01B11/27 , G01R1/073
CPC classification number: H01L22/32 , H01L23/544 , G01B11/272 , G01R1/073 , H01L2223/54426
Abstract: A system includes a wafer including at least an electronic component and a probe pad including a built-in back-end-of-line (BEOL) interconnect structure to test the electronic component. The electronic component is tested by the probe pad without building full BEOL interconnect circuits on the wafer. The probe pad is aligned with the wafer by using alignment marks. A prober alignment camera is employed to locate the alignment marks.
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公开(公告)号:US20230187284A1
公开(公告)日:2023-06-15
申请号:US17551266
申请日:2021-12-15
Applicant: International Business Machines Corporation
Inventor: Saumya Sharma , Ruturaj Nandkumar Pujari , Ashim Dutta , Chih-Chao Yang
CPC classification number: H01L22/12 , H01L21/67253 , H01L22/26 , H01L22/34
Abstract: Embodiments of the present invention are directed to in-situ wafer feedback schemes and systems for providing localized process-based compensation on a semiconductor wafer. In a non-limiting embodiment of the invention, a plurality of test structures are formed on a surface of a semiconductor wafer. The semiconductor wafer is placed under a detection surface of an in-situ feedback tool comprising one or more sensors. The in-situ feedback tool measures a property of each of the plurality of test structures and determines a local condition of the semiconductor wafer for each measured property of the plurality of test structures. A localized process-based compensation is provided on the surface of the semiconductor wafer for each local condition.
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