公开(公告)号：US20230197506A1

公开(公告)日：2023-06-22

申请号：US17552814

申请日：2021-12-16

Applicant: International Business Machines Corporation

Inventor： Saumya Sharma ,  Chih-Chao Yang ,  Tianji Zhou ,  Ashim Dutta

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76831 ,  H01L21/76897 ,  H01L21/76885 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53209

Abstract: Embodiments of the present invention are directed to subtractive processing methods and resulting structures for semiconductor devices having decoupled interconnects. In a non-limiting embodiment of the invention, a first conductive line is formed in a dielectric layer. A conductive pillar is formed over the first conductive line and a liner is formed in a trench adjacent to the first conductive line. A portion of the liner extends over the conductive pillar. A lower metal line and a top via are subtractively formed on the liner in the trench.

公开(公告)号：US20230187284A1

公开(公告)日：2023-06-15

申请号：US17551266

申请日：2021-12-15

Applicant: International Business Machines Corporation

Inventor： Saumya Sharma ,  Ruturaj Nandkumar Pujari ,  Ashim Dutta ,  Chih-Chao Yang

IPC: H01L21/66 ,  H01L21/67

CPC classification number: H01L22/12 ,  H01L21/67253 ,  H01L22/26 ,  H01L22/34

Abstract: Embodiments of the present invention are directed to in-situ wafer feedback schemes and systems for providing localized process-based compensation on a semiconductor wafer. In a non-limiting embodiment of the invention, a plurality of test structures are formed on a surface of a semiconductor wafer. The semiconductor wafer is placed under a detection surface of an in-situ feedback tool comprising one or more sensors. The in-situ feedback tool measures a property of each of the plurality of test structures and determines a local condition of the semiconductor wafer for each measured property of the plurality of test structures. A localized process-based compensation is provided on the surface of the semiconductor wafer for each local condition.

公开(公告)号：US20230081953A1

公开(公告)日：2023-03-16

申请号：US17447586

申请日：2021-09-14

Applicant: International Business Machines Corporation

Inventor： Saumya Sharma ,  Ashim Dutta ,  Tianji Zhou ,  Chih-Chao Yang

IPC: H01L23/528 ,  H01L21/768

Abstract: A semiconductor component includes an insulative layer having a lowermost surface arranged on top of a bottom dielectric material. The semiconductor component further includes a first interconnect structure arranged in the bottom dielectric material such that an uppermost surface of the first interconnect structure is arranged at a first height relative to the lowermost surface of the insulative layer. The semiconductor component further includes a pillar connected to the first interconnect structure and extending through the insulative layer. The semiconductor component further includes a second interconnect structure arranged in the bottom dielectric material such that an uppermost surface of the second interconnect structure is arranged at a second height relative to the lowermost surface of the insulative layer. The second height is different than the first height.

公开(公告)号：US11244907B2

公开(公告)日：2022-02-08

申请号：US16732531

申请日：2020-01-02

Applicant: International Business Machines Corporation

Inventor： Tianji Zhou ,  Saumya Sharma ,  Dominik Metzler ,  Chih-Chao Yang ,  Theodorus E. Standaert

IPC: H01L23/544 ,  G03F9/00

Abstract: Methods and structures for improving alignment contrast for patterning a metal layer generally includes depositing a metal layer having a plurality of grains, wherein grain boundaries between the grains forms grooves at a surface of the metal layer. The metal layer is subjected to surface treatment to form an oxide or a nitride layer and fill the surface grooves. The metal layer can be patterned using alignment marks in the metal layer and/or underlying layers. Filling the grooves with the oxide or nitride increases alignment contrast relative to patterning the metal layer without the surface treating.

公开(公告)号：US20210391256A1

公开(公告)日：2021-12-16

申请号：US16903213

申请日：2020-06-16

Applicant: International Business Machines Corporation

Inventor： Tianji Zhou ,  Saumya Sharma ,  Ashim DUTTA ,  Chih-Chao Yang

IPC: H01L23/525 ,  H01L23/522 ,  H01L23/532 ,  H01L23/528 ,  G11C17/18 ,  G11C17/16

Abstract: E-fuses and techniques for fabrication thereof using dielectric zipping are provided. An e-fuse device includes: a first dielectric layer disposed on a substrate; at least one first electrode of the e-fuse device present in the first dielectric layer; a second dielectric layer disposed on the first dielectric layer; vias present in the second dielectric layer, wherein at least one of the vias is present over the at least one first electrode and has a critical dimension CDA″, wherein the vias adjacent to the at least one via having the critical dimension CDA″ each have a critical dimension of CDB″, and wherein CDB″>CDA″; a liner disposed in each of the vias; and a metal that serves as a second electrode of the e-fuse device disposed in each of the vias over the liner. A method of operating an e-fuse device is also provided.

公开(公告)号：US20210375986A1

公开(公告)日：2021-12-02

申请号：US16886830

申请日：2020-05-29

Applicant: International Business Machines Corporation

Inventor： Ashim Dutta ,  Saumya Sharma ,  Tianji Zhou ,  Chih-Chao Yang

IPC: H01L27/22 ,  H01L43/12 ,  H01L43/02

Abstract: A technique relates to an integrated circuit (IC). Pillars of a set of memory elements are formed. A bilayer dielectric is formed between the pillars, the bilayer dielectric having an upper dielectric material formed on a lower dielectric material without requiring an etch of the lower dielectric material prior to forming the upper dielectric material, thereby preventing a void in the bilayer dielectric, the lower dielectric material including one or more flowable dielectric materials.

公开(公告)号：US20210358801A1

公开(公告)日：2021-11-18

申请号：US16874658

申请日：2020-05-14

Applicant: International Business Machines Corporation

Inventor： Ashim Dutta ,  Saumya Sharma ,  Tianji Zhou ,  Chih-Chao Yang

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528

Abstract: A method for making a semiconductor apparatus includes forming a first bottom interconnect in a device area of a first dielectric layer; fabricating a device on top of the first bottom interconnect; capping the device with a first interlayer dielectric; exposing a logic area of the first dielectric layer that is adjacent to the device area by removing a portion of the first interlayer dielectric from the first dielectric layer while leaving another portion of the first interlayer dielectric that caps the device; and forming a second bottom interconnect in the logic area of the first dielectric layer. By forming the second bottom interconnect after the device fabrication and capping, damage to the device and to the second bottom interconnect is avoided.

公开(公告)号：US20210233843A1

公开(公告)日：2021-07-29

申请号：US16774922

申请日：2020-01-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Chih-Chao Yang ,  Baozhen Li ,  Tianji Zhou ,  Ashim Dutta ,  Saumya Sharma

IPC: H01L23/525 ,  H01L23/522 ,  H01L21/768

Abstract: An anti-fuse device having enhanced programming efficiency is provided. The anti-fuse device includes via contact structures that have different critical dimensions located between a first electrode and a second electrode. Notably, a first via contact structure having a first critical dimension is provided between a pair of second via contact structures having a second critical dimension that is greater than the first critical dimension. When a voltage is applied to the device, dielectric breakdown will occur first through the first via contact structure having the first critical dimension.

公开(公告)号：US20230170266A1

公开(公告)日：2023-06-01

申请号：US17536228

申请日：2021-11-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ashim Dutta ,  Ruturaj Nandkumar Pujari ,  Saumya Sharma ,  Chih-Chao Yang

IPC: H01L21/66 ,  H01L23/544 ,  G01B11/27 ,  G01R1/073

CPC classification number: H01L22/32 ,  H01L23/544 ,  G01B11/272 ,  G01R1/073 ,  H01L2223/54426

Abstract: A system includes a wafer including at least an electronic component and a probe pad including a built-in back-end-of-line (BEOL) interconnect structure to test the electronic component. The electronic component is tested by the probe pad without building full BEOL interconnect circuits on the wafer. The probe pad is aligned with the wafer by using alignment marks. A prober alignment camera is employed to locate the alignment marks.

公开(公告)号：US11251368B2

公开(公告)日：2022-02-15

申请号：US16852997

申请日：2020-04-20

Applicant: International Business Machines Corporation

Inventor： Tianji Zhou ,  Saumya Sharma ,  Ashim Dutta ,  Chih-Chao Yang

IPC: H01L43/12 ,  H01L27/22 ,  H01L43/02

Abstract: A method includes forming a first metallization layer containing a first metal-containing line and a second metal-containing line disposed in a first interlevel dielectric layer. The first metal-containing line includes a first conductive metal and the second metal-containing line includes a second conductive metal. The first metal-containing line and the second metal-containing line are recessed to below a top surface of the interlevel dielectric layer. A metal-containing cap protection layer is deposited in a recessed portion of the first metal-containing line and the second metal-containing line. The metal-containing cap protection layer includes a third conductive metal which is different than the first conductive metal and the second conductive metal.