公开(公告)号：US20250120324A1

公开(公告)日：2025-04-10

申请号：US18483864

申请日：2023-10-10

Applicant: International Business Machines Corporation

Inventor： Oscar van der Straten ,  Chih-Chao Yang ,  Ashim Dutta ,  Wu-Chang Tsai ,  Ailian Zhao ,  Pei-I Wang ,  Shravana Kumar Katakam

IPC: H10N50/80 ,  G11C11/16 ,  H10B61/00 ,  H10N50/01 ,  H10N50/10

Abstract: A magnetoresistive random access memory (MRAM) includes a pillar structure having a bottom electrode and a magnetic tunnel junction (MTJ) having a reference layer, a free layer and a tunnel barrier disposed between the reference layer and the free layer. The MTJ is disposed on the bottom electrode. A top electrode is disposed on the MTJ. The top electrode includes two or more tiers wherein each tier successively includes a smaller footprint.

公开(公告)号：US20250062225A1

公开(公告)日：2025-02-20

申请号：US18451870

申请日：2023-08-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ashim Dutta ,  Chih-Chao Yang ,  Ailian Zhao ,  Wu-Chang Tsai

IPC: H01L23/525 ,  H01L23/528 ,  H01L23/532 ,  H01L23/62 ,  H01L21/768

Abstract: A fuse structure including a first conductive line and a second conductive line, a first metal pillar extending vertically from a top surface of the first conductive line and a second metal pillar extending vertically from a top surface of the second conductive line, a conductive link electrically connecting a top surface of the first metal pillar with a top surface of the second metal pillar, where both the first conductive line and the second conductive line are a different material than both the first metal pillar and the second metal pillar, and where both the first metal pillar and the second metal pillar are a different metal than the conductive link.

公开(公告)号：US20240421064A1

公开(公告)日：2024-12-19

申请号：US18334430

申请日：2023-06-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Chanro Park ,  Ruilong Xie ,  Julien Frougier ,  Chih-Chao Yang ,  Ashim Dutta ,  Shravana Kumar Katakam

IPC: H01L23/522

Abstract: A semiconductor device including a metal insulator metal capacitor (MIM capacitor) within back end of line circuitry, where a bottom electrode of the MIM capacitor includes a plurality of vertical pillars extending up from a bottom layer. A semiconductor device including a metal insulator metal capacitor (MIM capacitor), where a bottom electrode of the MIM capacitor includes a plurality of vertical pillars extending up from a bottom layer. Forming back end of line Mx-1 metal line layer, forming a plurality of Vx-1 via on the Mx-1 metal line layer, forming Mx metal line layer with subtractive patterning on the plurality of the Vx-1 via, forming a plurality of Vx via on the Mx metal line layer with subtractive patterning; and forming a block mask protecting a portion of the semiconductor device.

公开(公告)号：US12125790B2

公开(公告)日：2024-10-22

申请号：US17449381

申请日：2021-09-29

Applicant: International Business Machines Corporation

Inventor： Ashim Dutta ,  Ekmini Anuja De Silva ,  Praveen Joseph ,  Jennifer Church

IPC: H01L23/532 ,  H01L21/768

CPC classification number: H01L23/53295 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76837

Abstract: Airgap isolation for back-end-of-the-line interconnect structures includes a dielectric liner formed above a top surface and opposite sidewalls of each of a plurality of metal lines on a substrate, the dielectric liner disposed above a top surface of the substrate not covered by the plurality of metal lines, portions of the dielectric liner located on the opposite sidewalls of each of the plurality of metal lines are separated by a space. A dielectric cap is disposed above an uppermost surface of portions of the dielectric liner above each of the plurality of metal lines and above the space, the dielectric cap pinches-off the space between portions of the dielectric liner located on the opposite sidewalls of each of the plurality of metal lines for providing airgaps between adjacent metal lines.

公开(公告)号：US20240206345A1

公开(公告)日：2024-06-20

申请号：US18065651

申请日：2022-12-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ashim Dutta ,  Shravana Kumar Katakam ,  Chih-Chao Yang

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01

CPC classification number: H01L43/02 ,  H01L27/222 ,  H01L43/12

Abstract: A magnetic tunnel junction (MTJ) stack, and a metallic encapsulation layer surrounding vertical side surfaces of the MTJ stack, electrically and physically connected to a top electrode of the MTJ stack. A magnetic tunnel junction (MTJ) stack, and a metallic encapsulation layer surrounding vertical side surfaces of the MTJ stack, electrically and physically connected to a top electrode of the MTJ stack, where a lower horizontal surface of the metallic encapsulation layer is below a bottom electrode contact of the MTJ stack. Forming a magnetic tunnel junction (MTJ) stack and forming a metallic encapsulation layer surrounding vertical side surfaces of the MTJ stack, electrically and physically connected to a top electrode of the MTJ stack.

公开(公告)号：US20240188446A1

公开(公告)日：2024-06-06

申请号：US18061491

申请日：2022-12-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Shravana Kumar Katakam ,  Ashim Dutta ,  Chih-Chao Yang

IPC: H10N50/01 ,  G11C11/16 ,  H01L23/522 ,  H10B61/00 ,  H10N50/10 ,  H10N50/80

CPC classification number: H01L43/12 ,  G11C11/161 ,  G11C11/1657 ,  H01L23/5226 ,  H01L27/222 ,  H01L43/02 ,  H01L43/08

Abstract: A semiconductor device including a magnetic tunnel junction (MTJ) stack and an upper word line of the MTJ stack surrounding vertical side surfaces of the MTJ stack. A semiconductor device including a magnetic tunnel junction (MTJ) stack and an upper word line for the MTJ stack surrounding vertical side surfaces and an upper surface of a reference layer of the MTJ stack. A method including forming a forming a magnetic tunnel junction (MTJ) stack and forming a dielectric encapsulation layer surrounding vertical side surfaces of a top electrode, a free layer, a tunneling barrier, a reference layer and a bottom electrode of the MTJ stack.

公开(公告)号：US20240130242A1

公开(公告)日：2024-04-18

申请号：US18046162

申请日：2022-10-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ailian Zhao ,  Wu-Chang Tsai ,  Ashim Dutta ,  Chih-Chao Yang

IPC: H01L43/08 ,  H01L23/48 ,  H01L27/22 ,  H01L43/02 ,  H01L43/12

CPC classification number: H01L43/08 ,  H01L23/481 ,  H01L27/222 ,  H01L43/02 ,  H01L43/12

Abstract: Embodiments of present invention provide a method of forming a MRAM structure. The method includes forming at least one magnetic tunnel junction (MTJ) stack on top of a supporting structure; forming a conformal liner surrounding a sidewall of the MTJ stack; forming a first dielectric layer surrounding the conformal liner; selectively forming a metal oxide layer on top of the conformal liner and the first dielectric layer, the metal oxide layer having at least a first opening that exposes a top surface of the MTJ stack; and forming a top contact contacting the top surface of the MTJ stack through the first opening in the metal oxide layer. An MRAM structure formed thereby is also provided.

公开(公告)号：US20230290682A1

公开(公告)日：2023-09-14

申请号：US17691085

申请日：2022-03-09

Applicant: International Business Machines Corporation

Inventor： Ashim Dutta ,  Ekmini Anuja De Silva ,  Chih-Chao Yang ,  Jennifer Church

IPC: H01L21/768 ,  H01L23/528

CPC classification number: H01L21/76879 ,  H01L21/76865 ,  H01L23/5283 ,  H01L21/76801 ,  H01L21/76843 ,  H01L23/53266

Abstract: A semiconductor substrate has a metal via in the substrate, and has, on the substrate, a metal line that is less than 8 nanometers (nm) wide and at least 20 nm tall. A method for making a semiconductor structure includes forming a metal via in a substrate; forming a mandrel atop and offset from the via; depositing a metal-containing liner onto the mandrel; exposing the top of the mandrel by anisotropically etching the liner, thereby defining a separate portion of the liner at each side of the mandrel; and growing a metal line on each portion of the liner.

公开(公告)号：US20230197506A1

公开(公告)日：2023-06-22

申请号：US17552814

申请日：2021-12-16

Applicant: International Business Machines Corporation

Inventor： Saumya Sharma ,  Chih-Chao Yang ,  Tianji Zhou ,  Ashim Dutta

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76831 ,  H01L21/76897 ,  H01L21/76885 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53209

Abstract: Embodiments of the present invention are directed to subtractive processing methods and resulting structures for semiconductor devices having decoupled interconnects. In a non-limiting embodiment of the invention, a first conductive line is formed in a dielectric layer. A conductive pillar is formed over the first conductive line and a liner is formed in a trench adjacent to the first conductive line. A portion of the liner extends over the conductive pillar. A lower metal line and a top via are subtractively formed on the liner in the trench.

公开(公告)号：US20230187284A1

公开(公告)日：2023-06-15

申请号：US17551266

申请日：2021-12-15

Applicant: International Business Machines Corporation

Inventor： Saumya Sharma ,  Ruturaj Nandkumar Pujari ,  Ashim Dutta ,  Chih-Chao Yang

IPC: H01L21/66 ,  H01L21/67

CPC classification number: H01L22/12 ,  H01L21/67253 ,  H01L22/26 ,  H01L22/34

Abstract: Embodiments of the present invention are directed to in-situ wafer feedback schemes and systems for providing localized process-based compensation on a semiconductor wafer. In a non-limiting embodiment of the invention, a plurality of test structures are formed on a surface of a semiconductor wafer. The semiconductor wafer is placed under a detection surface of an in-situ feedback tool comprising one or more sensors. The in-situ feedback tool measures a property of each of the plurality of test structures and determines a local condition of the semiconductor wafer for each measured property of the plurality of test structures. A localized process-based compensation is provided on the surface of the semiconductor wafer for each local condition.