TRENCH LINER FUSE
    2.
    发明申请

    公开(公告)号:US20250062225A1

    公开(公告)日:2025-02-20

    申请号:US18451870

    申请日:2023-08-18

    Abstract: A fuse structure including a first conductive line and a second conductive line, a first metal pillar extending vertically from a top surface of the first conductive line and a second metal pillar extending vertically from a top surface of the second conductive line, a conductive link electrically connecting a top surface of the first metal pillar with a top surface of the second metal pillar, where both the first conductive line and the second conductive line are a different material than both the first metal pillar and the second metal pillar, and where both the first metal pillar and the second metal pillar are a different metal than the conductive link.

    METAL INSULATOR METAL CAPACITOR (MIM CAPACITOR)

    公开(公告)号:US20240421064A1

    公开(公告)日:2024-12-19

    申请号:US18334430

    申请日:2023-06-14

    Abstract: A semiconductor device including a metal insulator metal capacitor (MIM capacitor) within back end of line circuitry, where a bottom electrode of the MIM capacitor includes a plurality of vertical pillars extending up from a bottom layer. A semiconductor device including a metal insulator metal capacitor (MIM capacitor), where a bottom electrode of the MIM capacitor includes a plurality of vertical pillars extending up from a bottom layer. Forming back end of line Mx-1 metal line layer, forming a plurality of Vx-1 via on the Mx-1 metal line layer, forming Mx metal line layer with subtractive patterning on the plurality of the Vx-1 via, forming a plurality of Vx via on the Mx metal line layer with subtractive patterning; and forming a block mask protecting a portion of the semiconductor device.

    MRAM DEVICE WITH WRAP-AROUND TOP ELECTRODE CONTACT

    公开(公告)号:US20240206345A1

    公开(公告)日:2024-06-20

    申请号:US18065651

    申请日:2022-12-14

    CPC classification number: H01L43/02 H01L27/222 H01L43/12

    Abstract: A magnetic tunnel junction (MTJ) stack, and a metallic encapsulation layer surrounding vertical side surfaces of the MTJ stack, electrically and physically connected to a top electrode of the MTJ stack. A magnetic tunnel junction (MTJ) stack, and a metallic encapsulation layer surrounding vertical side surfaces of the MTJ stack, electrically and physically connected to a top electrode of the MTJ stack, where a lower horizontal surface of the metallic encapsulation layer is below a bottom electrode contact of the MTJ stack. Forming a magnetic tunnel junction (MTJ) stack and forming a metallic encapsulation layer surrounding vertical side surfaces of the MTJ stack, electrically and physically connected to a top electrode of the MTJ stack.

    IN-SITU FEEDBACK FOR LOCALIZED COMPENSATION
    10.
    发明公开

    公开(公告)号:US20230187284A1

    公开(公告)日:2023-06-15

    申请号:US17551266

    申请日:2021-12-15

    CPC classification number: H01L22/12 H01L21/67253 H01L22/26 H01L22/34

    Abstract: Embodiments of the present invention are directed to in-situ wafer feedback schemes and systems for providing localized process-based compensation on a semiconductor wafer. In a non-limiting embodiment of the invention, a plurality of test structures are formed on a surface of a semiconductor wafer. The semiconductor wafer is placed under a detection surface of an in-situ feedback tool comprising one or more sensors. The in-situ feedback tool measures a property of each of the plurality of test structures and determines a local condition of the semiconductor wafer for each measured property of the plurality of test structures. A localized process-based compensation is provided on the surface of the semiconductor wafer for each local condition.

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