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    DOPED CARBON NANOTUBES AND TRANSPARENT CONDUCTING FILMS CONTAINING THE SAME
    8.
    发明申请
    DOPED CARBON NANOTUBES AND TRANSPARENT CONDUCTING FILMS CONTAINING THE SAME 有权
    含有碳纳米管和透明导电膜

    公开(公告)号：US20150302950A1

    公开(公告)日：2015-10-22

    申请号：US14753236

    申请日：2015-06-29

    申请人： International Business Machines Corporation ,  Egypt Nanotechnology Center

    发明人： Mostafa M. El-Ashry ,  Ali Afzali-Ardakani ,  Bhupesh Chandra ,  George S. Tulevski

    IPC分类号： H01B1/24 ,  C01B31/02

    CPC分类号： H01B1/24 ,  B82Y30/00 ,  B82Y40/00 ,  C01B32/158 ,  C01B32/166 ,  C03C17/22 ,  C03C2217/28 ,  Y10S977/742 ,  Y10T428/30

    摘要： Transparent conducting electrodes include a doped single walled carbon nanotube film and methods for forming the doped single walled carbon nanotube (SWCNT) by solution processing. The method generally includes depositing single walled carbon nanotubes dispersed in a solvent and a surfactant onto a substrate to form a single walled carbon nanotube film thereon; removing all of the surfactant from the carbon nanotube film; and exposing the single walled carbon nanotube film to a single electron oxidant in a solution such that one electron is transferred from the single walled carbon nanotubes to each molecule of the single electron oxidant.

    摘要翻译： 透明导电电极包括掺杂的单壁碳纳米管膜和通过溶液处理形成掺杂的单壁碳纳米管（SWCNT）的方法。 该方法通常包括将分散在溶剂中的单壁碳纳米管和表面活性剂沉积在基底上以在其上形成单壁碳纳米管膜; 从碳纳米管膜中除去所有的表面活性剂; 并将单壁碳纳米管膜暴露于溶液中的单一电子氧化剂，使得一个电子从单壁碳纳米管转移到单一电子氧化剂的每个分子。

    Faceted intrinsic epitaxial buffer layer for reducing short channel effects while maximizing channel stress levels
    9.
    发明授权
    Faceted intrinsic epitaxial buffer layer for reducing short channel effects while maximizing channel stress levels 有权
    方面的本征外延缓冲层，用于减少短通道效应，同时最大化通道应力水平

    公开(公告)号：US08940595B2

    公开(公告)日：2015-01-27

    申请号：US13839741

    申请日：2013-03-15

    申请人： International Business Machines Corporation

    发明人： Bhupesh Chandra ,  Paul Chang ,  Gregory G. Freeman ,  Dechao Guo ,  Judson R. Holt ,  Arvind Kumar ,  Timothy J. McArdle ,  Shreesh Narasimha ,  Viorel Ontalus ,  Sangameshwar Rao Saudari ,  Christopher D. Sheraw ,  Matthew W. Stoker

    IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L29/66

    CPC分类号： H01L29/7848 ,  H01L29/045 ,  H01L29/165 ,  H01L29/36 ,  H01L29/66636 ,  H01L29/7834

    摘要： A faceted intrinsic buffer semiconductor material is deposited on sidewalls of a source trench and a drain trench by selective epitaxy. A facet adjoins each edge at which an outer sidewall of a gate spacer adjoins a sidewall of the source trench or the drain trench. A doped semiconductor material is subsequently deposited to fill the source trench and the drain trench. The doped semiconductor material can be deposited such that the facets of the intrinsic buffer semiconductor material are extended and inner sidewalls of the deposited doped semiconductor material merges in each of the source trench and the drain trench. The doped semiconductor material can subsequently grow upward. Faceted intrinsic buffer semiconductor material portions allow greater outdiffusion of dopants near faceted corners while suppressing diffusion of dopants in regions of uniform width, thereby suppressing short channel effects.

    摘要翻译： 通过选择性外延法将刻面的本征缓冲半导体材料沉积在源沟槽和漏极沟槽的侧壁上。 一个刻面邻接每个边缘，栅极间隔件的外侧壁邻接源沟槽或漏极沟槽的侧壁。 随后沉积掺杂的半导体材料以填充源极沟槽和漏极沟槽。 可以沉积掺杂的半导体材料，使得本征缓冲半导体材料的面被延伸，并且沉积的掺杂半导体材料的内壁在源极沟槽和漏极沟槽的每一个中融合。 掺杂的半导体材料随后可以向上生长。 方面的本征缓冲半导体材料部分允许在均匀宽度的区域中抑制掺杂剂的扩散，从而抑制短沟道效应，从而在小角部附近进一步扩散掺杂剂。

    N-dopant for carbon nanotubes and graphene
    10.
    发明授权
    N-dopant for carbon nanotubes and graphene 有权
    碳纳米管和石墨烯的N掺杂剂

    公开(公告)号：US09105853B2

    公开(公告)日：2015-08-11

    申请号：US14051869

    申请日：2013-10-11

    申请人： International Business Machines Corporation

    发明人： Ali Afzali-Ardakani ,  Bhupesh Chandra ,  George Stojan Tulevski

    IPC分类号： H01L21/336 ,  H01L51/05 ,  B82Y10/00 ,  H01L51/00 ,  B82Y40/00

    CPC分类号： H01L51/0558 ,  B82Y10/00 ,  B82Y40/00 ,  H01L51/0018 ,  H01L51/002 ,  H01L51/0048 ,  H01L51/0072 ,  H01L51/055 ,  Y10S977/846 ,  Y10S977/938

    摘要： A composition and method for forming a field effect transistor with a stable n-doped nano-component. The method includes forming a gate dielectric on a gate, forming a channel comprising a nano-component on the gate dielectric, forming a source over a first region of the nano-component, forming a drain over a second region of the nano-component to form a field effect transistor, and exposing a portion of a nano-component of a field effect transistor to dihydrotetraazapentacene, wherein dihydrotetraazapentacene is represented by the formula: wherein each of R1, R2, R3, and R4 comprises one of hydrogen, an alkyl group of C1 to C16 carbons, an alkoxy group, an alkylthio group, a trialkylsilane group, a hydroxymethyl group, a carboxylic acid group and a carboxylic ester group.

    摘要翻译： 用于形成具有稳定的n掺杂纳米组分的场效应晶体管的组合物和方法。 该方法包括在栅极上形成栅极电介质，在栅极电介质上形成包含纳米成分的沟道，在纳米元件的第一区域上形成源极，在纳米元件的第二区域上形成漏极， 形成场效应晶体管，并将场效应晶体管的纳米组分的一部分暴露于二氢四氮杂，其中二氢四氮杂苯由下式表示：其中R1，R2，R3和R4各自包含氢，烷基 C1〜C16碳，烷氧基，烷硫基，三烷基硅烷基，羟甲基，羧酸基和羧酸酯基。