公开(公告)号：US20040108913A1

公开(公告)日：2004-06-10

申请号：US10315836

申请日：2002-12-10

Applicant: Intersil Americas Inc.

Inventor： Lawrence G. Pearce ,  William David Bartlett

IPC: H03K007/08

CPC classification number: H03L7/0805 ,  H03K5/06 ,  H03K7/08 ,  H03L7/0812

Abstract: A tapped delay line generates a fractional clock pulse signal for controlling a PWM pulse generator, such as used in a DC-DC converter. Operational parameters of the tapped delay are adjusted to maintain a desired fractional precision of the duty-cycle of the PWM clock pulse signal. In a first, phase locked loop (PLL) based embodiment, the tapped delay line-based digital PWM pulse generator includes a compensating phase locked-loop formed around an auxiliary tapped delay line that implements the voltage controlled oscillator of the PLL. In a second embodiment, the PWM pulse generator is configured as an nullopen-loopnull tapped delay line phase detector architecture, which avoids having to correlate parameters of the PLL delay line with those of the PWM delay line.

Abstract translation: 抽头延迟线产生用于控制PWM脉冲发生器的分数时钟脉冲信号，例如在DC-DC转换器中使用的。 调整抽头延迟的操作参数以保持PWM时钟脉冲信号占空比的期望分数精度。 在基于锁相环（PLL）的第一实施例中，基于抽头的延迟线数字PWM脉冲发生器包括一个形成在辅助抽头延迟线周围的补偿锁相环，该延迟线实现PLL的压控振荡器。 在第二实施例中，PWM脉冲发生器被配置为“开环”抽头延迟线相位检测器架构，避免了将PLL延迟线的参数与PWM延迟线的参数相关联。

公开(公告)号：US20040146101A1

公开(公告)日：2004-07-29

申请号：US10350599

申请日：2003-01-24

Applicant: Intersil Americas Inc.

Inventor： Lawrence G. Pearce

IPC: H03K007/08 ,  H03K009/08

CPC classification number: H03K5/133 ,  H02M3/157 ,  H03K7/08 ,  H03K2005/00058 ,  H03L7/00

Abstract: A digitally-implemented pulse width modulation (PWM) signal generator forms the PWM pulse width as a rational number based on full cycles of a PWM reference clock, and offers a very high effective resolution of the PWM pulse signal that is compatible with multiphase DC-DC converters. Being totally digital allows digital error accumulation and correction to occur at the point of origin of the PWM signal, well upstream of the relatively slow voltage control feedback loop. Quantization errors are corrected before they can accumulate in the converter's DC output voltage.

Abstract translation: 数字实现的脉冲宽度调制（PWM）信号发生器基于PWM参考时钟的全周期形成PWM脉冲宽度作为有理数，并提供与多相DC-DC相兼容的PWM脉冲信号的非常高的有效分辨率， DC转换器。 完全数字化允许数字错误累积和校正发生在PWM信号的原点，在相对较慢的电压控制反馈回路的上游。 量化误差在它们可以在转换器的直流输出电压中积累之前被校正。

公开(公告)号：US20040145360A1

公开(公告)日：2004-07-29

申请号：US10350755

申请日：2003-01-24

Applicant: Intersil Americas Inc.

Inventor： Lawrence G. Pearce ,  Nicolaas W. Van Vonno

IPC: G05F001/40

CPC classification number: H02J1/102 ,  H02M3/1584

Abstract: An electronic device may include a circuit board, at least one load circuit carried by the circuit board, and a power distribution conductor carried by the circuit board and connected to the at least one load circuit. The electronic device may also include a multiphase switching regulator including a plurality of output stages connected to the power distribution conductor, and a controller for controlling the output stages based upon respective phase currents. The respective phase currents may be derived from corresponding voltage drops across the power distribution conductor and a matrix of resistivity values.

Abstract translation: 电子设备可以包括电路板，由电路板承载的至少一个负载电路和由电路板承载并连接到至少一个负载电路的配电导体。 电子设备还可以包括多相开关调节器，其包括连接到配电导体的多个输出级，以及用于基于各自的相电流来控制输出级的控制器。 相应的相电流可以从功率分布导体上的相应电压降和电阻率值矩阵导出。

公开(公告)号：US20040125968A1

公开(公告)日：2004-07-01

申请号：US10738590

申请日：2003-12-15

Applicant: Intersil Americas Inc.

Inventor： Lawrence G. Pearce ,  Donald F. Hemmenway

IPC: H04R003/00 ,  H03F021/00

CPC classification number: H01L21/8234 ,  H01L21/8249 ,  H01L27/0207 ,  H01L27/0623 ,  H01L27/0922 ,  H01L29/0615 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/665 ,  H01L29/66719 ,  H01L29/7809 ,  H01L29/7811 ,  H01L29/7815 ,  H03F1/523 ,  H03F3/187 ,  H03F3/217 ,  H03F3/2171 ,  H03F3/2173 ,  H03F3/72

Abstract: A monolithic 1.75 is mounted in a speaker cabinet 1.71 to drive the voice coil 1.74 of the speaker 1.70. The monolithic integrated circuit may be a class D amplifier 1.10, and is at least a half-bridge or full bridge power MOSFET device. Structures and process for forming the mos switching devices 2.20 of the bridge driver circuits are disclosed. Also disclosed is the Nnull buried layer 4.14 of the QVDMOS transistors 4.43 of the bridge circuits.

Abstract translation: 单体1.75安装在扬声器箱1.71中以驱动扬声器1.70的音圈1.74。 单片集成电路可以是D类放大器1.10，并且是至少一个半桥或全桥功率MOSFET器件。 公开了用于形成桥式驱动器电路的mos开关器件2.20的结构和工艺。 还公开了桥接电路的QVDMOS晶体管4.43的N +掩埋层4.14。