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公开(公告)号：US20160224450A1
公开(公告)日：2016-08-04
申请号：US15012707
申请日：2016-02-01
申请人： Invecas, Inc.
发明人： Kevin W. Gorman , Thomas Chadwick , Nancy Pratt
IPC分类号： G06F11/27
CPC分类号： G06F11/263 , G11C29/14 , G11C29/16 , G11C2029/0401
摘要： A memory built-in self test (“BIST”) system comprises: a controller; a single port memory engine coupled to one or more single port memories; and a non-single port memory engine coupled to one or more non-single port memories. The controller receives operation codes (“op-codes”) for testing a plurality of memory types. An output of the controller is coupled to inputs of the single port memory engine and the non-single port memory engine. The controller generates test instructions based on the received op-codes. The single port memory engine and the non-single port memory engine interpret the test instructions to test the one or more single port memories and the one or more non-single port memories.
摘要翻译： 内存自检（“BIST”）系统包括：控制器; 耦合到一个或多个单个端口存储器的单个端口存储器引擎; 以及耦合到一个或多个非单一端口存储器的非单端口存储器引擎。 控制器接收用于测试多种存储器类型的操作代码（“操作代码”）。 控制器的输出耦合到单端口存储器引擎和非单端口存储器引擎的输入。 控制器根据接收的操作码产生测试指令。 单端口存储器引擎和非单端口存储器引擎解释测试指令以测试一个或多个单端口存储器和一个或多个非单端口存储器。
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公开(公告)号：US20170316837A1
公开(公告)日：2017-11-02
申请号：US15140242
申请日：2016-04-27
申请人： Invecas, Inc.
发明人： Thomas Chadwick , Kevin W. Gorman , Nancy Pratt
CPC分类号： G11C29/38 , G11C29/44 , G11C2029/3202
摘要： A memory diagnostic system comprises a test engine and a miscompare logic. The test engine provides test instructions with expected data to a memory under test (“MUT”). The MUT processes such test patterns and outputs the results of such test patterns as stored data. The miscompare logic has local miscompare logics and a global miscompare logic. Each of the local miscompare logics compares a predefined range of bits of the expected data with a corresponding predefined range of bits of the stored data. One or more miscompare flags are generated for one or more miscompares determined by the local miscompare logics. The global miscompare logic monitors the one or more miscompare flags. When a total number of the miscompare flags exceeds a threshold number, the global miscompare logic generates a pause signal to the local miscompare logics to capture a current state of the local miscompare logics.
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公开(公告)号：US09946620B2
公开(公告)日：2018-04-17
申请号：US15012707
申请日：2016-02-01
申请人： Invecas, Inc.
发明人： Kevin W. Gorman , Thomas Chadwick , Nancy Pratt
CPC分类号： G06F11/263 , G11C29/14 , G11C29/16 , G11C2029/0401
摘要： A memory built-in self test (“BIST”) system comprises: a controller; a single port memory engine coupled to one or more single port memories; and a non-single port memory engine coupled to one or more non-single port memories. The controller receives operation codes (“op-codes”) for testing a plurality of memory types. An output of the controller is coupled to inputs of the single port memory engine and the non-single port memory engine. The controller generates test instructions based on the received op-codes. The single port memory engine and the non-single port memory engine interpret the test instructions to test the one or more single port memories and the one or more non-single port memories.
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公开(公告)号：US09865361B2
公开(公告)日：2018-01-09
申请号：US15140242
申请日：2016-04-27
申请人： Invecas, Inc.
发明人： Thomas Chadwick , Kevin W. Gorman , Nancy Pratt
CPC分类号： G11C29/38 , G11C29/44 , G11C2029/3202
摘要： A memory diagnostic system comprises a test engine and a miscompare logic. The test engine provides test instructions with expected data to a memory under test (“MUT”). The MUT processes such test patterns and outputs the results of such test patterns as stored data. The miscompare logic has local miscompare logics and a global miscompare logic. Each of the local miscompare logics compares a predefined range of bits of the expected data with a corresponding predefined range of bits of the stored data. One or more miscompare flags are generated for one or more miscompares determined by the local miscompare logics. The global miscompare logic monitors the one or more miscompare flags. When a total number of the miscompare flags exceeds a threshold number, the global miscompare logic generates a pause signal to the local miscompare logics to capture a current state of the local miscompare logics.
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公开(公告)号：US09799413B2
公开(公告)日：2017-10-24
申请号：US15012721
申请日：2016-02-01
申请人： Invecas, Inc.
发明人： Kevin W. Gorman , Thomas Chadwick , Nancy Pratt
CPC分类号： G11C29/785 , G11C2029/4402
摘要： A fuse controller comprises: a fuse bay, a bus, an engine, and an interface. The fuse bay stores repair and setting information for a plurality of fuse domains in a linked-list data structure. The engine manages the linked-list data structure. The engine also is coupled to the fuse domains via the bus. The interface is coupled to the engine and receives commands and data for operating the engine.
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公开(公告)号：US20160224451A1
公开(公告)日：2016-08-04
申请号：US15012721
申请日：2016-02-01
申请人： Invecas, Inc.
发明人： Kevin W. Gorman , Thomas Chadwick , Nancy Pratt
IPC分类号： G06F11/27
CPC分类号： G11C29/785 , G11C2029/4402
摘要： A fuse controller comprises: a fuse bay, a bus, an engine, and an interface. The fuse bay stores repair and setting information for a plurality of fuse domains in a linked-list data structure. The engine manages the linked-list data structure. The engine also is coupled to the fuse domains via the bus. The interface is coupled to the engine and receives commands and data for operating the engine.
摘要翻译： 保险丝控制器包括：保险丝架，总线，发动机和接口。 保险丝架以链接列表数据结构存储多个熔丝域的修复和设置信息。 引擎管理链表数据结构。 引擎还通过总线耦合到熔丝域。 该接口连接到发动机并接收用于操作发动机的命令和数据。
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