公开(公告)号：US20180173600A1

公开(公告)日：2018-06-21

申请号：US15849468

申请日：2017-12-20

Applicant: Invensas Corporation

Inventor： Javier A. DELACRUZ ,  Steven L. TEIG ,  David Edward FISCH ,  William C. PLANTS

IPC: G06F11/26 ,  G06F11/22 ,  H01L25/00 ,  H01L25/18 ,  H01L23/00

Abstract: This disclosure pertains to hardware compute arrays (sometimes called systolic arrays) for applications such as artificial intelligence (AI), machine learning (ML), digital signal processing (DSP), graphics processing units (GPUs), and other computationally intensive applications. More particularly, it pertains to novel and advantageous architecture innovations for efficiently and inexpensively implementing such arrays using multiple integrated circuits. Hardware and methods are disclosed to allow compute arrays to be tested after face-to-face or wafer-to-wafer bonding and without out any pre-bonding test. Defects discovered in the post-bonding testing can be completely or partially healed increasing yields and reducing costs.

公开(公告)号：US20180180665A1

公开(公告)日：2018-06-28

申请号：US15388130

申请日：2016-12-22

Applicant: Invensas Corporation

Inventor： Javier A. DELACRUZ ,  William C. PLANTS

IPC: G01R31/28

CPC classification number: G01R31/2856 ,  G01R31/2831 ,  G01R31/2884 ,  G01R31/2894

Abstract: The invention pertains to in-wafer testing of integrated circuits. In particular, it pertains to apparatuses and methods for testing small integrated circuits that have pad sizes and pitches that are too small for using conventional wafer probing technology.

公开(公告)号：US20180177041A1

公开(公告)日：2018-06-21

申请号：US15387278

申请日：2016-12-21

Applicant: Invensas Corporation

Inventor： Shaowu HUANG ,  Javier A. DELACRUZ

IPC: H05K1/02 ,  H01P3/16 ,  H03H1/00 ,  H01P1/20 ,  H01P1/38 ,  H03H7/38 ,  H01P11/00 ,  H05K3/30

CPC classification number: H05K1/0228 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01P1/2088 ,  H01P1/39 ,  H01P3/121 ,  H01P5/19 ,  H01P7/065 ,  H01P11/002 ,  H01Q13/18 ,  H05K3/30 ,  H05K2201/10287 ,  H01L2924/00014

Abstract: Apparatus, and corresponding method, relates generally to a microelectronic device. In such an apparatus, a first conductive layer is for providing a lower interior surface of a circuit structure. A plurality of wire bond wires are interconnected to the lower interior surface and spaced apart from one another for providing at least one side of the circuit structure. A second conductive layer is for providing an upper interior surface of the circuit structure spaced apart from the lower interior surface by and interconnected to the plurality of wire bond wires. The plurality of wire bond wires, the first conductive layer and the second conductive layer in combination define at least one opening in the at least one side for a signal port of the circuit structure. Such circuit structure may be a signal guide circuit structure, such as for a signal waveguide or signal cavity for example.