公开(公告)号：US20180173600A1

公开(公告)日：2018-06-21

申请号：US15849468

申请日：2017-12-20

Applicant: Invensas Corporation

Inventor： Javier A. DELACRUZ ,  Steven L. TEIG ,  David Edward FISCH ,  William C. PLANTS

IPC: G06F11/26 ,  G06F11/22 ,  H01L25/00 ,  H01L25/18 ,  H01L23/00

Abstract: This disclosure pertains to hardware compute arrays (sometimes called systolic arrays) for applications such as artificial intelligence (AI), machine learning (ML), digital signal processing (DSP), graphics processing units (GPUs), and other computationally intensive applications. More particularly, it pertains to novel and advantageous architecture innovations for efficiently and inexpensively implementing such arrays using multiple integrated circuits. Hardware and methods are disclosed to allow compute arrays to be tested after face-to-face or wafer-to-wafer bonding and without out any pre-bonding test. Defects discovered in the post-bonding testing can be completely or partially healed increasing yields and reducing costs.

公开(公告)号：US20180180665A1

公开(公告)日：2018-06-28

申请号：US15388130

申请日：2016-12-22

Applicant: Invensas Corporation

Inventor： Javier A. DELACRUZ ,  William C. PLANTS

IPC: G01R31/28

CPC classification number: G01R31/2856 ,  G01R31/2831 ,  G01R31/2884 ,  G01R31/2894

Abstract: The invention pertains to in-wafer testing of integrated circuits. In particular, it pertains to apparatuses and methods for testing small integrated circuits that have pad sizes and pitches that are too small for using conventional wafer probing technology.

公开(公告)号：US20160314042A1

公开(公告)日：2016-10-27

申请号：US14876069

申请日：2015-10-06

Applicant: Invensas Corporation

Inventor： William C. PLANTS

IPC: G06F11/10 ,  G06F3/06 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0656 ,  G06F3/0679 ,  G06F3/0688 ,  G11C29/52 ,  G11C2029/0411

Abstract: The invention pertains to non-volatile memory devices, and more particularly to advantageously encoding data in non-volatile devices in a flexible manner by both NVM manufacturers and NVM users. Multiple methods of preferred state encoding (PSE) and/or error correction code (ECC) encoding may be used in different pages or blocks in the same NVM device for different purposes which may be dependent on the nature of the data to be stored.

Abstract translation: 本发明涉及非易失性存储器件，并且更具体地涉及有利地由NVM制造商和NVM用户以灵活的方式对非易失性器件中的数据进行编码。 优选状态编码（PSE）和/或纠错码（ECC）编码的多种方法可以用于相同NVM设备中的不同页面或块，用于不同目的，这可能取决于要存储的数据的性质。

公开(公告)号：US20140313834A1

公开(公告)日：2014-10-23

申请号：US13868884

申请日：2013-04-23

Applicant: Invensas Corporation

Inventor： David Edward FISCH ,  William C. PLANTS ,  Kent STALNAKER

IPC: G11C29/52

CPC classification number: G11C11/4091 ,  G11C7/00 ,  G11C7/02 ,  G11C7/062 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/1069 ,  G11C7/1096 ,  G11C11/4087 ,  G11C11/4096 ,  G11C29/52

Abstract: A method for storing data. The method includes providing an addressable memory including a memory space, wherein the memory space includes a plurality of memory cells. The method includes configuring the addressable memory such that a majority of the plurality of memory cells in the memory space stores internal data values in a preferred bias condition when a first external data state of one or more external data states is written to the memory space, wherein the first external data state is opposite the preferred bias condition.

Abstract translation: 一种存储数据的方法。 该方法包括提供包括存储器空间的可寻址存储器，其中存储器空间包括多个存储器单元。 该方法包括配置可寻址存储器，使得当将一个或多个外部数据状态的第一外部数据状态写入存储器空间时，存储器空间中的多个存储器单元的大部分将内部数据值存储在优选偏置条件中， 其中所述第一外部数据状态与所述偏好条件相反。