公开(公告)号：US08619236B2

公开(公告)日：2013-12-31

申请号：US12953511

申请日：2010-11-24

Applicant: James A. Bruce ,  Edward W. Conrad ,  Jacek G. Smolinski

Inventor： James A. Bruce ,  Edward W. Conrad ,  Jacek G. Smolinski

IPC: G03B27/32 ,  G03B27/68 ,  G03B27/52 ,  G03B27/42

CPC classification number: G03F1/36 ,  G03F7/705

Abstract: The subject matter disclosed herein relates to determining a lithographic set point using simulations of optical proximity correction verification. In one embodiment, a computer-implemented method of determining a lithographic tool set point for a lithographic process is disclosed. The method may include: providing a model of a production lithographic process including simulations of printed shapes; analyzing the model of the production lithographic process to determine whether a set of structures on a production mask used in the production lithographic process to create the printed shapes will fail under a plurality of set points; determining an operating region of set points where the set of structures on the production mask does not fail; and establishing a set point location within the operating region based upon a set point selection function.

Abstract translation: 本文公开的主题涉及使用光学邻近校正验证的模拟来确定光刻设置点。 在一个实施例中，公开了一种用于确定光刻工艺的光刻工具设定点的计算机实现的方法。 该方法可以包括：提供生产平版印刷工艺的模型，包括印刷形状的模拟; 分析生产光刻工艺的模型，以确定在生产光刻工艺中用于产生印刷形状的生产掩模上的一组结构是否将在多个设定点下失效; 确定生产掩模上的一组结构不失败的设定点的操作区域; 以及基于设定点选择功能在操作区域内建立设定点位置。

公开(公告)号：US20110173586A1

公开(公告)日：2011-07-14

申请号：US12687147

申请日：2010-01-14

Applicant: James A. Bruce ,  Edward W. Conrad ,  Jacek G. Smolinski

Inventor： James A. Bruce ,  Edward W. Conrad ,  Jacek G. Smolinski

IPC: G06F17/50

CPC classification number: G03F1/44 ,  G03F1/36 ,  G03F1/84 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides a method and computer program product for designing an electrically testable pattern that is based on patterns derived from the desired chip layout to be printed. Such electrical test patterns are based on the features within a region of influence around critical sites. The critical sites may be identified, for example, by processing the chip layout through an OPC verification tool that flags potential failure sites. The electrical test pattern is formed from features within an region of influence (ROI) around the critical site, and also include electrical feed lines at terminal ends of one or more features having an electrical characteristic that is sensitive to changes in the printed environment of the critical site. The feed lines may be locate on the same or a different layer than the critical site, depending on the chip design. The electrical pattern is further defined by retaining features within a second trim region such that the printed features within the ROI are not substantially modified by the absence of features outside the second trim region.

Abstract translation: 本发明提供一种用于设计基于从要打印的所需芯片布局导出的图案的电可测图案的方法和计算机程序产品。 这种电气测试模式基于围绕关键场所的影响区域内的特征。 可以通过例如标记潜在故障位置的OPC验证工具来处理芯片布局来识别关键位置。 电测试图案由围绕关键位置的影响区域（ROI）内的特征形成，并且还包括在一个或多个特征的终端处的电馈线，其具有对于印刷环境的变化敏感的电特性 关键站点。 取决于芯片设计，馈线可以位于与关键位置相同或不同的层上。 通过在第二修剪区域内保持特征来进一步限定电气图案，使得ROI内的印刷特征基本上不被第二修剪区域外的特征缺失地修改。

公开(公告)号：US20120127442A1

公开(公告)日：2012-05-24

申请号：US12953511

申请日：2010-11-24

Applicant: JAMES A. BRUCE ,  Edward W. Conrad ,  Jacek G. Smolinski

Inventor： JAMES A. BRUCE ,  Edward W. Conrad ,  Jacek G. Smolinski

IPC: G03B27/42

CPC classification number: G03F1/36 ,  G03F7/705

Abstract: The subject matter disclosed herein relates to determining a lithographic set point using simulations of optical proximity correction verification. In one embodiment, a computer-implemented method of determining a lithographic tool set point for a lithographic process is disclosed. The method may include: providing a model of a production lithographic process including simulations of printed shapes; analyzing the model of the production lithographic process to determine whether a set of structures on a production mask used in the production lithographic process to create the printed shapes will fail under a plurality of set points; determining an operating region of set points where the set of structures on the production mask does not fail; and establishing a set point location within the operating region based upon a set point selection function.

Abstract translation: 本文公开的主题涉及使用光学邻近校正验证的模拟来确定光刻设置点。 在一个实施例中，公开了一种用于确定光刻工艺的光刻工具设定点的计算机实现的方法。 该方法可以包括：提供生产平版印刷工艺的模型，包括印刷形状的模拟; 分析生产光刻工艺的模型，以确定在生产光刻工艺中用于产生印刷形状的生产掩模上的一组结构是否将在多个设定点下失效; 确定生产掩模上的一组结构不失败的设定点的操作区域; 以及基于设定点选择功能在操作区域内建立设定点位置。

公开(公告)号：US08219964B2

公开(公告)日：2012-07-10

申请号：US12687147

申请日：2010-01-14

Applicant: James A. Bruce ,  Edward W. Conrad ,  Jacek G. Smolinski

Inventor： James A. Bruce ,  Edward W. Conrad ,  Jacek G. Smolinski

IPC: G06F17/50

CPC classification number: G03F1/44 ,  G03F1/36 ,  G03F1/84 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides a method and computer program product for designing an electrically testable pattern that is based on patterns derived from the desired chip layout to be printed. Such electrical test patterns are based on the features within a region of influence around critical sites. The critical sites may be identified, for example, by processing the chip layout through an OPC verification tool that flags potential failure sites. The electrical test pattern is formed from features within an region of influence (ROI) around the critical site, and also include electrical feed lines at terminal ends of one or more features having an electrical characteristic that is sensitive to changes in the printed environment of the critical site. The feed lines may be locate on the same or a different layer than the critical site, depending on the chip design. The electrical pattern is further defined by retaining features within a second trim region such that the printed features within the ROI are not substantially modified by the absence of features outside the second trim region.

Abstract translation: 本发明提供一种用于设计基于从要打印的所需芯片布局导出的图案的电可测图案的方法和计算机程序产品。 这种电气测试模式基于围绕关键场所的影响区域内的特征。 可以通过例如标记潜在故障位置的OPC验证工具来处理芯片布局来识别关键位置。 电测试图案由围绕关键位置的影响区域（ROI）内的特征形成，并且还包括在一个或多个特征的终端处的电馈线，其具有对于印刷环境的变化敏感的电特性 关键站点。 取决于芯片设计，馈线可以位于与关键位置相同或不同的层上。 通过在第二修剪区域内保持特征来进一步限定电气图案，使得ROI内的印刷特征基本上不被第二修剪区域外的特征缺失地修改。

公开(公告)号：US07269808B2

公开(公告)日：2007-09-11

申请号：US10908786

申请日：2005-05-26

Applicant: James A. Bruce ,  James A. Culp ,  John D. Nickel ,  Jacek G. Smolinski

Inventor： James A. Bruce ,  James A. Culp ,  John D. Nickel ,  Jacek G. Smolinski

IPC: G06F17/50

CPC classification number: G06F17/5081

Abstract: A design verification method, including (a) providing in a design a design electrically conducting line and a design contact region being in direct physical contact with the design electrically conducting line; (b) modeling a simulated electrically conducting line of the design electrically conducting line; (c) simulating a possible contact region of the design contact region, wherein the design contact region and the possible contact region are not identical; and (d) determining that the design electrically conducting line and the design contact region are potentially defective if an interfacing surface area of the simulated electrically conducting line and the possible contact region is less than a pre-specified value.

Abstract translation: 一种设计验证方法，包括（a）在设计中提供与设计导电线直接物理接触的设计导电线和设计接触区; （b）对设计导电线的模拟导电线进行建模; （c）模拟设计接触区域的可能的接触区域，其中设计接触区域和可能的接触区域不相同; 以及（d）如果所述模拟导电线路和所述可能接触区域的接口表面积小于预定值，则确定所述设计导电线路和所述设计接触区域具有潜在的缺陷。

公开(公告)号：US20080141211A1

公开(公告)日：2008-06-12

申请号：US11609033

申请日：2006-12-11

Applicant: James A. Bruce ,  Gregory J. Dick ,  Donald P. Perley ,  Jacek G. Smolinski

Inventor： James A. Bruce ,  Gregory J. Dick ,  Donald P. Perley ,  Jacek G. Smolinski

IPC: G06F17/50

CPC classification number: G03F1/36

Abstract: A method is provided for performing optical proximity correction (“OPC”) verification in which features of concern of a photomask are identified using data relating to shapes of the photomask, an aerial image to be obtained using the photomask, or a photoresist image to be obtained in a photoimageable layer using the photomask. A plurality of areas of the photomask, aerial image or photoresist image are identified which incorporate the identified features of concern, where the plurality of identified areas occupy substantially less area than the total area of the photomask that is occupied by features. Enhanced OPC verification limited to the plurality of identified areas is then performed to identify problems of at least one of the photomask, aerial image or photoresist image.

Abstract translation: 提供了一种用于执行光学邻近校正（“OPC”）验证的方法，其中使用与光掩模的形状，使用光掩模获得的空间图像或光致抗蚀剂图像相关联的数据来识别光掩模的特征 使用光掩模在可光成像层中获得。 识别光掩模，空中图像或光致抗蚀剂图像的多个区域，其包含所识别的关注特征，其中多个识别区域占据占据特征的光掩模的总面积的面积实质上更小的面积。 然后执行限于多个所识别的区域的增强的OPC验证，以识别光掩模，空中图像或光致抗蚀剂图像中的至少一个的问题。

公开(公告)号：US07562337B2

公开(公告)日：2009-07-14

申请号：US11609033

申请日：2006-12-11

Applicant: James A. Bruce ,  Gregory J. Dick ,  Donald P. Perley ,  Jacek G. Smolinski

Inventor： James A. Bruce ,  Gregory J. Dick ,  Donald P. Perley ,  Jacek G. Smolinski

IPC: G06F17/50 ,  G06F19/00 ,  G03F1/00 ,  G21K5/00 ,  G06K9/00

CPC classification number: G03F1/36

Abstract: A method is provided for performing optical proximity correction (“OPC”) verification in which features of concern of a photomask are identified using data relating to shapes of the photomask, an aerial image to be obtained using the photomask, or a photoresist image to be obtained in a photoimageable layer using the photomask. A plurality of areas of the photomask, aerial image or photoresist image are identified which incorporate the identified features of concern, where the plurality of identified areas occupy substantially less area than the total area of the photomask that is occupied by features. Enhanced OPC verification limited to the plurality of identified areas is then performed to identify problems of at least one of the photomask, aerial image or photoresist image.

Abstract translation: 提供了一种用于执行光学邻近校正（“OPC”）验证的方法，其中使用与光掩模的形状，使用光掩模获得的空间图像或光致抗蚀剂图像相关联的数据来识别光掩模的特征 使用光掩模在可光成像层中获得。 识别光掩模，空中图像或光致抗蚀剂图像的多个区域，其包含所识别的关注特征，其中多个识别区域占据占据特征的光掩模的总面积的面积实质上更小的面积。 然后执行限于多个所识别的区域的增强的OPC验证，以识别光掩模，空中图像或光致抗蚀剂图像中的至少一个的问题。

公开(公告)号：US6156461A

公开(公告)日：2000-12-05

申请号：US504031

申请日：2000-02-14

Applicant: Brian J. Grenon ,  Richard A. Haight ,  Dennis M. Hayden ,  Michael S. Hibbs ,  J. Peter Levin ,  Timothy E. Neary ,  Raymond E. Rochefort ,  Dennis A. Schmidt ,  Jacek G. Smolinski ,  Alfred Wagner

Inventor： Brian J. Grenon ,  Richard A. Haight ,  Dennis M. Hayden ,  Michael S. Hibbs ,  J. Peter Levin ,  Timothy E. Neary ,  Raymond E. Rochefort ,  Dennis A. Schmidt ,  Jacek G. Smolinski ,  Alfred Wagner

IPC: B23K26/06 ,  G03F1/74 ,  H01L21/027 ,  G03S9/00

CPC classification number: G03F1/74 ,  B23K26/0624

Abstract: A method of repairing defects on masks includes the step of providing a coating on the mask to prevent damage to clear regions of the mask from laser ablation splatter, laser ablation caused quartz pitting, laser deposition staining, and FIB caused gallium staining. The coating is a metal, a polymer, or a carbon material. The coating is formed on clear regions of the mask as well as either over or under the light absorbing material of the mask. A coating comprising a thin copper layer significantly improves imaging with the ion beam while protecting clear regions of the mask from FIB stain. A coating formed of a photosensitive polymer is used to etch opaque defects. While wanted opaque regions adjacent an opaque defect are also etched in this etch step, these created clear defects are then repaired in a subsequent FIB deposition step while a copper coating protects adjacent clear regions from FIB stain. In another embodiment, opaque defects are repaired with a short pulse duration laser without damage to underlying quartz or adjacent clear regions while avoiding the need for a coating.

Abstract translation: 修复掩模上的缺陷的方法包括在掩模上提供涂层以防止由于激光烧蚀溅射，激光烧蚀引起的石英点蚀，激光沉积染色和FIB引起的镓染色而对掩模的清晰区域的损害的步骤。 涂层是金属，聚合物或碳材料。 涂层形成在掩模的透明区域以及掩模的光吸收材料的上方或下方。 包含薄铜层的涂层显着地改善了用离子束的成像，同时保护掩模的清除区域不受FIB染色。 由光敏聚合物形成的涂层用于蚀刻不透明缺陷。 虽然在该蚀刻步骤中也蚀刻邻近不透明缺陷的不透明区域，然后在随后的FIB沉积步骤中修复这些产生的明确缺陷，而铜涂层保护相邻的清晰区域免受FIB染色。 在另一个实施例中，用短脉冲持续时间激光修复不透明缺陷，而不损害下面的石英或相邻的透明区域，同时避免了涂层的需要。

公开(公告)号：US07434185B2

公开(公告)日：2008-10-07

申请号：US11535789

申请日：2006-09-27

Applicant: Daria R. Dooling ,  Kenneth T. Settlemyer, Jr. ,  Jacek G. Smolinski ,  Stephen D. Thomas ,  Ralph J. Williams

Inventor： Daria R. Dooling ,  Kenneth T. Settlemyer, Jr. ,  Jacek G. Smolinski ,  Stephen D. Thomas ,  Ralph J. Williams

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G03F1/36

Abstract: A method for implementing an ORC process to facilitate physical verification of an integrated circuit (IC) graphical design. The method includes partitioning the IC graphical design data into files by a host machine such that the files correspond to regions of interest or partitions with defined margins, dispersing the partitioned data files to available cpus within the network, processing of each job by the cpu receiving the file, wherein artifacts arising from bisection of partitioning margins during the partitioning, including cut-induced false errors, are detected and removed, and the shape-altering effects of such artifact errors are minimized and transmitting the results of processing at each cpu to the host machine for aggregate processing.

Abstract translation: 一种用于实现ORC过程以促进集成电路（IC）图形设计的物理验证的方法。 该方法包括：通过主机将IC图形设计数据划分成文件，使得文件对应于具有定义边距的感兴趣区域或分区，将分割的数据文件分散到网络内的可用CPU，通过cpu接收处理每个作业 文件，其中检测和去除在划分期间由分割边缘的二分分割产生的伪像，包括切割引起的错误错误，并且将这些伪像误差的形状改变效果最小化，并将每个cpu处理的结果传送到 主机用于聚合处理。

公开(公告)号：US20080077891A1

公开(公告)日：2008-03-27

申请号：US11535789

申请日：2006-09-27

Applicant: Daria R. Dooling ,  Kenneth T. Settlemyer ,  Jacek G. Smolinski ,  Stephen D. Thomas ,  Ralph J. Williams

Inventor： Daria R. Dooling ,  Kenneth T. Settlemyer ,  Jacek G. Smolinski ,  Stephen D. Thomas ,  Ralph J. Williams

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G03F1/36

Abstract: A method for implementing an ORC process to facilitate physical verification of an integrated circuit (IC) graphical design. The method includes partitioning the IC graphical design data into files by a host machine such that the files correspond to regions of interest or partitions with defined margins, dispersing the partitioned data files to available cpus within the network, processing of each job by the cpu receiving the file, wherein artifacts arising from bisection of partitioning margins during the partitioning, including cut-induced false errors, are detected and removed, and the shape-altering effects of such artifact errors are minimized and transmitting the results of processing at each cpu to the host machine for aggregate processing.

Abstract translation: 一种用于实现ORC过程以促进集成电路（IC）图形设计的物理验证的方法。 该方法包括：通过主机将IC图形设计数据划分成文件，使得文件对应于具有定义边距的感兴趣区域或分区，将分割的数据文件分散到网络内的可用CPU，通过cpu接收处理每个作业 文件，其中检测和去除在划分期间由分割边缘的二分分割产生的伪像，包括切割引起的错误错误，并且将这些伪像误差的形状改变效果最小化，并将每个cpu处理的结果传送到 主机用于聚合处理。