公开(公告)号：US20120127442A1

公开(公告)日：2012-05-24

申请号：US12953511

申请日：2010-11-24

Applicant: JAMES A. BRUCE ,  Edward W. Conrad ,  Jacek G. Smolinski

Inventor： JAMES A. BRUCE ,  Edward W. Conrad ,  Jacek G. Smolinski

IPC: G03B27/42

CPC classification number: G03F1/36 ,  G03F7/705

Abstract: The subject matter disclosed herein relates to determining a lithographic set point using simulations of optical proximity correction verification. In one embodiment, a computer-implemented method of determining a lithographic tool set point for a lithographic process is disclosed. The method may include: providing a model of a production lithographic process including simulations of printed shapes; analyzing the model of the production lithographic process to determine whether a set of structures on a production mask used in the production lithographic process to create the printed shapes will fail under a plurality of set points; determining an operating region of set points where the set of structures on the production mask does not fail; and establishing a set point location within the operating region based upon a set point selection function.

Abstract translation: 本文公开的主题涉及使用光学邻近校正验证的模拟来确定光刻设置点。 在一个实施例中，公开了一种用于确定光刻工艺的光刻工具设定点的计算机实现的方法。 该方法可以包括：提供生产平版印刷工艺的模型，包括印刷形状的模拟; 分析生产光刻工艺的模型，以确定在生产光刻工艺中用于产生印刷形状的生产掩模上的一组结构是否将在多个设定点下失效; 确定生产掩模上的一组结构不失败的设定点的操作区域; 以及基于设定点选择功能在操作区域内建立设定点位置。

公开(公告)号：US08619236B2

公开(公告)日：2013-12-31

申请号：US12953511

申请日：2010-11-24

Applicant: James A. Bruce ,  Edward W. Conrad ,  Jacek G. Smolinski

Inventor： James A. Bruce ,  Edward W. Conrad ,  Jacek G. Smolinski

IPC: G03B27/32 ,  G03B27/68 ,  G03B27/52 ,  G03B27/42

CPC classification number: G03F1/36 ,  G03F7/705

Abstract: The subject matter disclosed herein relates to determining a lithographic set point using simulations of optical proximity correction verification. In one embodiment, a computer-implemented method of determining a lithographic tool set point for a lithographic process is disclosed. The method may include: providing a model of a production lithographic process including simulations of printed shapes; analyzing the model of the production lithographic process to determine whether a set of structures on a production mask used in the production lithographic process to create the printed shapes will fail under a plurality of set points; determining an operating region of set points where the set of structures on the production mask does not fail; and establishing a set point location within the operating region based upon a set point selection function.

Abstract translation: 本文公开的主题涉及使用光学邻近校正验证的模拟来确定光刻设置点。 在一个实施例中，公开了一种用于确定光刻工艺的光刻工具设定点的计算机实现的方法。 该方法可以包括：提供生产平版印刷工艺的模型，包括印刷形状的模拟; 分析生产光刻工艺的模型，以确定在生产光刻工艺中用于产生印刷形状的生产掩模上的一组结构是否将在多个设定点下失效; 确定生产掩模上的一组结构不失败的设定点的操作区域; 以及基于设定点选择功能在操作区域内建立设定点位置。

公开(公告)号：US20110173586A1

公开(公告)日：2011-07-14

申请号：US12687147

申请日：2010-01-14

Applicant: James A. Bruce ,  Edward W. Conrad ,  Jacek G. Smolinski

Inventor： James A. Bruce ,  Edward W. Conrad ,  Jacek G. Smolinski

IPC: G06F17/50

CPC classification number: G03F1/44 ,  G03F1/36 ,  G03F1/84 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides a method and computer program product for designing an electrically testable pattern that is based on patterns derived from the desired chip layout to be printed. Such electrical test patterns are based on the features within a region of influence around critical sites. The critical sites may be identified, for example, by processing the chip layout through an OPC verification tool that flags potential failure sites. The electrical test pattern is formed from features within an region of influence (ROI) around the critical site, and also include electrical feed lines at terminal ends of one or more features having an electrical characteristic that is sensitive to changes in the printed environment of the critical site. The feed lines may be locate on the same or a different layer than the critical site, depending on the chip design. The electrical pattern is further defined by retaining features within a second trim region such that the printed features within the ROI are not substantially modified by the absence of features outside the second trim region.

Abstract translation: 本发明提供一种用于设计基于从要打印的所需芯片布局导出的图案的电可测图案的方法和计算机程序产品。 这种电气测试模式基于围绕关键场所的影响区域内的特征。 可以通过例如标记潜在故障位置的OPC验证工具来处理芯片布局来识别关键位置。 电测试图案由围绕关键位置的影响区域（ROI）内的特征形成，并且还包括在一个或多个特征的终端处的电馈线，其具有对于印刷环境的变化敏感的电特性 关键站点。 取决于芯片设计，馈线可以位于与关键位置相同或不同的层上。 通过在第二修剪区域内保持特征来进一步限定电气图案，使得ROI内的印刷特征基本上不被第二修剪区域外的特征缺失地修改。

公开(公告)号：US08219964B2

公开(公告)日：2012-07-10

申请号：US12687147

申请日：2010-01-14

Applicant: James A. Bruce ,  Edward W. Conrad ,  Jacek G. Smolinski

Inventor： James A. Bruce ,  Edward W. Conrad ,  Jacek G. Smolinski

IPC: G06F17/50

CPC classification number: G03F1/44 ,  G03F1/36 ,  G03F1/84 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides a method and computer program product for designing an electrically testable pattern that is based on patterns derived from the desired chip layout to be printed. Such electrical test patterns are based on the features within a region of influence around critical sites. The critical sites may be identified, for example, by processing the chip layout through an OPC verification tool that flags potential failure sites. The electrical test pattern is formed from features within an region of influence (ROI) around the critical site, and also include electrical feed lines at terminal ends of one or more features having an electrical characteristic that is sensitive to changes in the printed environment of the critical site. The feed lines may be locate on the same or a different layer than the critical site, depending on the chip design. The electrical pattern is further defined by retaining features within a second trim region such that the printed features within the ROI are not substantially modified by the absence of features outside the second trim region.

Abstract translation: 本发明提供一种用于设计基于从要打印的所需芯片布局导出的图案的电可测图案的方法和计算机程序产品。 这种电气测试模式基于围绕关键场所的影响区域内的特征。 可以通过例如标记潜在故障位置的OPC验证工具来处理芯片布局来识别关键位置。 电测试图案由围绕关键位置的影响区域（ROI）内的特征形成，并且还包括在一个或多个特征的终端处的电馈线，其具有对于印刷环境的变化敏感的电特性 关键站点。 取决于芯片设计，馈线可以位于与关键位置相同或不同的层上。 通过在第二修剪区域内保持特征来进一步限定电气图案，使得ROI内的印刷特征基本上不被第二修剪区域外的特征缺失地修改。

公开(公告)号：US07257247B2

公开(公告)日：2007-08-14

申请号：US09683836

申请日：2002-02-21

Applicant: James A. Bruce ,  Orest Bula ,  Edward W. Conrad ,  William C. Leipold ,  Michael S. Hibbs ,  Joshua J. Krueger

Inventor： James A. Bruce ,  Orest Bula ,  Edward W. Conrad ,  William C. Leipold ,  Michael S. Hibbs ,  Joshua J. Krueger

IPC: G06K9/00

CPC classification number: G03F1/84

Abstract: An automated system for analyzing mask defects in a semiconductor manufacturing process is presented. This system combines results from an inspection tool and design layout data from a design data repository corresponding to each mask layer being inspected with a computer program and a predetermined rule set to determine when a defect on a given mask layer has occurred. Mask inspection results include the presence, location and type (clear or opaque) of defects. Ultimately, a determination is made as to whether to scrap, repair or accept a given mask based on whether the defect would be likely to cause product failure. Application of the defect inspection data to the design layout data for each mask layer being inspected prevents otherwise acceptable wafer masks from being scrapped when the identified defects are not in critical areas of the mask.

Abstract translation: 提出了一种用于分析半导体制造过程中的掩模缺陷的自动化系统。 该系统将来自检查工具的结果和来自被检查的每个掩模层的设计数据存储库的设计布局数据与计算机程序和预定规则集相结合，以确定给定掩模层上的缺陷何时发生。 掩模检查结果包括缺陷的存在，位置和类型（透明或不透明）。 最终，根据缺陷是否可能导致产品故障，确定是否废除，修理或接受给定的掩模。 将缺陷检查数据应用于被检查的每个掩模层的设计布局数据防止当所识别的缺陷不在掩模的关键区域时被报废。

公开(公告)号：US07492941B2

公开(公告)日：2009-02-17

申请号：US11769431

申请日：2007-06-27

Applicant: James A. Bruce ,  Orest Bula ,  Edward W. Conrad ,  William C. Leipold ,  Michael S. Hibbs ,  Joshua J. Krueger

Inventor： James A. Bruce ,  Orest Bula ,  Edward W. Conrad ,  William C. Leipold ,  Michael S. Hibbs ,  Joshua J. Krueger

IPC: G06K9/00

CPC classification number: G03F1/84

Abstract: An automated system for analyzing mask defects in a semiconductor manufacturing process is presented. This system combines results from an inspection tool and design layout data from a design data repository corresponding to each mask layer being inspected with a computer program and a predetermined rule set to determine when a defect on a given mask layer has occurred. Mask inspection results include the presence, location and type (clear or opaque) of defects. Ultimately, a determination is made as to whether to scrap, repair or accept a given mask based on whether the defect would be likely to cause product failure. Application of the defect inspection data to the design layout data for each mask layer being inspected prevents otherwise acceptable wafer masks from being scrapped when the identified defects are not in critical areas of the mask.

公开(公告)号：US07492940B2

公开(公告)日：2009-02-17

申请号：US11761856

申请日：2007-06-12

Applicant: James A. Bruce ,  Orest Bula ,  Edward W. Conrad ,  William C. Leipold ,  Michael S. Hibbs ,  Joshua J. Krueger

Inventor： James A. Bruce ,  Orest Bula ,  Edward W. Conrad ,  William C. Leipold ,  Michael S. Hibbs ,  Joshua J. Krueger

IPC: G06K9/00

CPC classification number: G03F1/84

Abstract: An automated system for analyzing mask defects in a semiconductor manufacturing process is presented. This system combines results from an inspection tool and design layout data from a design data repository corresponding to each mask layer being inspected with a computer program and a predetermined rule set to determine when a defect on a given mask layer has occurred. Mask inspection results include the presence, location and type (clear or opaque) of defects. Ultimately, a determination is made as to whether to scrap, repair or accept a given mask based on whether the defect would be likely to cause product failure. Application of the defect inspection data to the design layout data for each mask layer being inspected prevents otherwise acceptable wafer masks from being scrapped when the identified defects are not in critical areas of the mask.

Abstract translation: 提出了一种用于分析半导体制造过程中的掩模缺陷的自动化系统。 该系统将来自检查工具的结果和来自被检查的每个掩模层的设计数据存储库的设计布局数据与计算机程序和预定规则集相结合，以确定何时发生了给定掩模层上的缺陷。 掩模检查结果包括缺陷的存在，位置和类型（透明或不透明）。 最终，根据缺陷是否可能导致产品故障，确定是否废除，修理或接受给定的掩模。 将缺陷检查数据应用于被检查的每个掩模层的设计布局数据防止当所识别的缺陷不在掩模的关键区域时被报废。

公开(公告)号：US06395438B1

公开(公告)日：2002-05-28

申请号：US09756540

申请日：2001-01-08

Applicant: James A. Bruce ,  Orest Bula ,  Edward W. Conrad ,  William C. Leipold

Inventor： James A. Bruce ,  Orest Bula ,  Edward W. Conrad ,  William C. Leipold

IPC: G03F900

CPC classification number: G03F1/36 ,  G03F1/80 ,  G03F7/70433

Abstract: A method for including etch bias corrections in pre-processing of integrated circuit design data to compensate for deviations introduced during lithographic printing and etching. The design data is segmented, and etch bias corrections are applied to the segments based on their proximity to adjacent design features. Adjusted or corrected design data is produced which may be used to create a mask which includes etch bias corrections for better fidelity and reproduction of the original design in the etching step. Etch bias corrections may also be applied based upon characteristics of regions defined in the design, or on a pattern density of the design.

Abstract translation: 一种在集成电路设计数据的预处理中包括蚀刻偏差校正以补偿在平版印刷和蚀刻期间引入的偏差的方法。 设计数据被分段，并且基于它们与相邻设计特征的接近度，将蚀刻偏差校正应用于段。 产生调整或校正的设计数据，其可用于创建掩模，该掩模包括用于在蚀刻步骤中更好保真度和再现原始设计的蚀刻偏差校正。 也可以基于设计中定义的区域的特征或设计的图案密度来应用蚀刻偏差校正。

公开(公告)号：US06539321B2

公开(公告)日：2003-03-25

申请号：US09906919

申请日：2001-07-17

Applicant: James A. Bruce ,  Orest Bula ,  Edward W. Conrad ,  William C. Leipold

Inventor： James A. Bruce ,  Orest Bula ,  Edward W. Conrad ,  William C. Leipold

IPC: G06F1900

CPC classification number: G03F7/70508 ,  G03F7/70516 ,  G03F7/70608 ,  G03F7/70625

Abstract: Method for effecting edge bias correction of topography-induced linewidth variations which are encountered in printed or integrated circuits on substrates or semiconductor devices for electronic packages. The method modifies data for current levels which is predicated on prior level data and models, as to the manner in which topography will affect the resist and/or antireflective coating (ARC) thicknesses, so as to improve upon linewidth (LW) control and, in general, imparting improved processing windows. The method can be implemented in the form of computer-executable instructions which are embodied in one or more program modules stored on computer-usable media.

Abstract translation: 用于对用于电子封装的衬底或半导体器件上的印刷或集成电路中遇到的形貌诱导线宽变化的边缘偏置校正的方法。 该方法修改了基于先前水平数据和模型的当前水平的数据，关于形貌将影响抗蚀剂和/或抗反射涂层（ARC）厚度的方式，以便改进线宽（LW）控制， 一般来说，赋予改进的处理窗口。 该方法可以以存储在计算机可用介质上的一个或多个程序模块中体现的计算机可执行指令的形式来实现。

公开(公告)号：US06694498B2

公开(公告)日：2004-02-17

申请号：US10016552

申请日：2001-12-13

Applicant: Edward W. Conrad ,  Charles J. Parrish ,  Charles A. Whiting

Inventor： Edward W. Conrad ,  Charles J. Parrish ,  Charles A. Whiting

IPC: G06F1750

CPC classification number: G03F7/70633

Abstract: A method and system embodying the present invention for predicting systematic overlay affects in semiconductor lithography. This method is a feed-forward method, based on correlation of current and prior aligned levels, to predict optimum overlay offsets for a given lot. Instead of using population averaging, which ignores process variability, it acknowledges the variability and uses prior measurements to advantage. The principle, backed by production data, is that “systematic” overlay errors are just that: Image placement errors which persist through processing and will be predictable through time and processing.

Abstract translation: 体现本发明的用于预测半导体光刻中的系统叠加影响的方法和系统。 该方法是基于当前和先前对齐水平的相关性的预测方法，以预测给定批次的最佳叠加偏移。 而不是使用人口平均，忽略过程变异性，它承认变异性，并使用先前的测量。 以生产数据为基础的原则是“系统”重叠错误就是：通过处理持续存在的图像放置错误，并且可以通过时间和处理来预测。