公开(公告)号：US20160276365A1

公开(公告)日：2016-09-22

申请号：US15066619

申请日：2016-03-10

申请人： JI-HOON CHOI ,  SEUNGHYUN LIM ,  SUNGGIL KIM ,  HONGSUK KIM ,  HUNHYEONG LIM ,  HYUNJUN SIM

发明人： JI-HOON CHOI ,  SEUNGHYUN LIM ,  SUNGGIL KIM ,  HONGSUK KIM ,  HUNHYEONG LIM ,  HYUNJUN SIM

IPC分类号： H01L27/115 ,  H01L29/10

CPC分类号： H01L27/11582 ,  H01L27/11565 ,  H01L27/1157

摘要： A semiconductor memory device includes a stack including gate electrodes sequentially stacked on a substrate, a vertical insulating structure penetrating the stack vertically with respect to the gate electrodes, a vertical channel portion disposed on an inner side surface of the vertical insulating structure, and a common source region formed in the substrate and spaced apart from the vertical channel portion. A bottom region of the vertical channel portion has a protruding surface in contact with a bottom region of the vertical insulating structure.

摘要翻译： 一种半导体存储器件包括：堆叠，其包括依次层叠在基板上的栅极电极，相对于栅电极垂直地贯穿堆叠体的垂直绝缘结构，设置在垂直绝缘结构的内侧面的垂直沟道部， 源极区域形成在衬底中并且与垂直沟道部分间隔开。 垂直通道部分的底部区域具有与垂直绝缘结构的底部区域接触的突出表面。

公开(公告)号：US20160240550A1

公开(公告)日：2016-08-18

申请号：US15043640

申请日：2016-02-15

申请人： JAEHUN JUNG ,  ZHILIANG XIA ,  DAEWOONG KANG ,  DAE SIN KIM ,  KWANG SOO SEOL ,  HOMIN SON ,  SEUNGHYUN LIM

发明人： JAEHUN JUNG ,  ZHILIANG XIA ,  DAEWOONG KANG ,  DAE SIN KIM ,  KWANG SOO SEOL ,  HOMIN SON ,  SEUNGHYUN LIM

IPC分类号： H01L27/115 ,  H01L29/792 ,  H01L29/423

CPC分类号： H01L27/11568 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/4234 ,  H01L29/42364 ,  H01L29/512 ,  H01L29/517 ,  H01L29/518 ,  H01L29/792 ,  H01L29/7923

摘要： A non-volatile memory device includes gate electrodes stacked on a substrate, a semiconductor pattern penetrating the gate electrodes and connected to the substrate, and a charge storage layer between the semiconductor pattern and the gate electrodes. The charge storage layer includes a first charge storage layer between the semiconductor pattern and the gate electrodes, a second charge storage layer between the first charge storage layer and the semiconductor pattern, and a third charge storage layer between the first charge storage layer and the gate electrodes. An energy band gap of the first charge storage layer is smaller than those of the second and third charge storage layers. The first charge storage layer is thicker than the second and third charge storage layers.

摘要翻译： 非易失性存储器件包括堆叠在衬底上的栅极电极，穿过栅极并连接到衬底的半导体图案，以及半导体图案和栅电极之间的电荷存储层。 电荷存储层包括半导体图形和栅电极之间的第一电荷存储层，第一电荷存储层和半导体图案之间的第二电荷存储层，以及第一电荷存储层和栅极之间的第三电荷存储层 电极。 第一电荷存储层的能带隙比第二和第三电荷存储层的能带隙小。 第一电荷存储层比第二和第三电荷存储层厚。

公开(公告)号：US20160351582A1

公开(公告)日：2016-12-01

申请号：US15165135

申请日：2016-05-26

申请人： Nambin Kim ,  DAEWOONG KANG ,  DAE SIN KIM ,  KWANG SOO SEOL ,  HOMIN SON ,  CHANGSUB LEE ,  SEUNGHYUN LIM ,  SUNGHOI HUR

发明人： Nambin Kim ,  DAEWOONG KANG ,  DAE SIN KIM ,  KWANG SOO SEOL ,  HOMIN SON ,  CHANGSUB LEE ,  SEUNGHYUN LIM ,  SUNGHOI HUR

IPC分类号： H01L27/115 ,  H01L29/792

CPC分类号： H01L27/11582 ,  H01L27/1157

摘要： Provided is a semiconductor device including a substrate, gate electrodes vertically stacked on the substrate, insulating patterns between the gate electrodes, an active pillar provided to penetrate the gate electrodes and the insulating patterns and electrically coupled with the substrate, and a memory pattern provided between the gate electrodes and the active pillar and between the insulating patterns and the active pillar. The gate electrodes include edge portions extending between the memory pattern and the insulating patterns.

摘要翻译： 本发明提供一种半导体器件，包括基板，垂直堆叠在基板上的栅电极，栅电极之间的绝缘图案，设置成穿过栅电极的活性柱和绝缘图案，并与基板电耦合，以及存储图案， 栅电极和有源支柱以及绝缘图案和有源支柱之间。 栅电极包括在存储器图案和绝缘图案之间延伸的边缘部分。

公开(公告)号：US20160225786A1

公开(公告)日：2016-08-04

申请号：US14993485

申请日：2016-01-12

申请人： HYUN-WOOK LEE ,  DAEWOONG KANG ,  DAE SIN KIM ,  KWANG SOO SEOL ,  HOMIN SON ,  SEUNGHYUN LIM

发明人： HYUN-WOOK LEE ,  DAEWOONG KANG ,  DAE SIN KIM ,  KWANG SOO SEOL ,  HOMIN SON ,  SEUNGHYUN LIM

IPC分类号： H01L27/115 ,  H01L29/423

CPC分类号： H01L27/11582 ,  H01L21/28282 ,  H01L27/11556 ,  H01L29/4234 ,  H01L29/42348

摘要： A semiconductor device includes a stack comprising insulating patterns vertically stacked on a substrate and gate patterns interposed between the insulating patterns, an active pillar passing through the stack and electrically connected to the substrate and a charge storing layer interposed between the stack and the active pillar. The charge storing layer includes a first portion between the active pillar and one of the gate patterns, a second portion between the active pillar and one of the insulating patterns, and a third portion joining the first portion to the second portion and having a thickness less than that of the first portion.

摘要翻译： 半导体器件包括堆叠，其包括垂直堆叠在衬底上的绝缘图案和插入在绝缘图案之间的栅极图案，穿过堆叠并电连接到衬底的有源柱和插入在堆叠和有源柱之间的电荷存储层。 电荷存储层包括在有源支柱和一个栅极图案之间的第一部分，在有源支柱和一个绝缘图案之间的第二部分，以及将第一部分连接到第二部分并且具有较小厚度的第三部分 比第一部分。