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    SEMICONDUCTOR DEVICE HAVING CHANNEL HOLES
    3.
    发明申请
    SEMICONDUCTOR DEVICE HAVING CHANNEL HOLES 有权
    具有通道孔的半导体器件

    公开(公告)号：US20170047342A1

    公开(公告)日：2017-02-16

    申请号：US15173888

    申请日：2016-06-06

    申请人： SUNG MIN HWANG ,  Jang Gn Yun ,  Ahn Sik Moon ,  Se Jun Park ,  Zhiliang Xia ,  Joon Sung Lim

    发明人： SUNG MIN HWANG ,  Jang Gn Yun ,  Ahn Sik Moon ,  Se Jun Park ,  Zhiliang Xia ,  Joon Sung Lim

    IPC分类号： H01L27/115 ,  H01L23/528 ,  H01L23/522

    CPC分类号： H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573

    摘要： A semiconductor device includes a gate stack including gate electrodes stacked vertically on a substrate. Channel holes penetrate through the gate stack to extend vertically to the substrate. Each of the channel holes includes a channel region. First channel pads are each disposed at an end of a respective channel hole opposite the substrate. Each of the first channel pads includes at least one first conductivity-type impurity. Second channel pads are each disposed at an end of a respective channel hole opposite the substrate. Each of the second channel pads includes at least one second conductivity-type impurity.

    摘要翻译： 半导体器件包括栅极堆叠，其包括垂直堆叠在衬底上的栅电极。 通道孔穿过栅极堆叠，以垂直于衬底延伸。 每个通道孔包括通道区域。 第一通道焊盘各自设置在与衬底相对的相应通道孔的端部。 每个第一通道焊盘包括至少一种第一导电型杂质。 第二通道焊盘各自设置在与衬底相对的相应通道孔的端部。 每个第二通道焊盘包括至少一个第二导电类型的杂质。

    TEST METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR TEST APPARATUS
    4.
    发明申请
    TEST METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR TEST APPARATUS 有权
    半导体器件和半导体测试装置的测试方法

    公开(公告)号：US20140133254A1

    公开(公告)日：2014-05-15

    申请号：US14060808

    申请日：2013-10-23

    申请人： Chiho KIM ,  Zhiliang XIA ,  Sung Hee LEE ,  Nara KIM ,  Dae Sin KIM

    发明人： Chiho KIM ,  Zhiliang XIA ,  Sung Hee LEE ,  Nara KIM ,  Dae Sin KIM

    IPC分类号： G11C29/08

    CPC分类号： G11C29/50016 ,  G11C11/40 ,  G11C29/50 ,  G11C29/56

    摘要： A test method of a semiconductor device and a semiconductor test apparatus. The test method includes providing a semiconductor device including a substrate having an active region and an isolation region, a volatile device cell including a gate insulation layer and a gate on the active region, a junction region in the active region, a capacitor connected to the junction region, and a passing gate on the isolation region, providing a first test voltage to the gate and a second test voltage greater than the first test voltage to the passing gate to deteriorate interfacial defects of the gate insulation layer, and measuring retention characteristics of the volatile device cell.

    摘要翻译： 半导体器件和半导体测试装置的测试方法。 测试方法包括提供包括具有有源区和隔离区的衬底的半导体器件，在有源区上包括栅极绝缘层和栅极的易失性器件单元，有源区中的结区，连接到 并且在隔离区域上具有通过栅极，向栅极提供第一测试电压，并且对通过栅极提供大于第一测试电压的第二测试电压，以降低栅极绝缘层的界面缺陷，并测量保留特性 易失性器件单元。

    SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME
    6.
    发明申请
    SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME 有权
    半导体器件及其制造方法

    公开(公告)号：US20170069636A1

    公开(公告)日：2017-03-09

    申请号：US15160335

    申请日：2016-05-20

    申请人： Se-Jun PARK ,  Jang-Gn Yun ,  Sung-Min Hwang ,  Ahn-Sik Moon ,  Zhiliang Xia

    发明人： Se-Jun PARK ,  Jang-Gn Yun ,  Sung-Min Hwang ,  Ahn-Sik Moon ,  Zhiliang Xia

    IPC分类号： H01L27/115 ,  H01L23/528 ,  H01L21/768 ,  H01L23/522

    CPC分类号： H01L27/1157 ,  H01L27/11582

    摘要： A semiconductor device includes a plurality of insulation patterns and a plurality of gates alternately and repeatedly stacked on a substrate, a channel pattern extending through the gates in a first direction substantially perpendicular to a top surface of the substrate, a semiconductor pattern between the channel pattern and the substrate, and a conductive pattern between the channel pattern and the semiconductor pattern. The conductive pattern electrically connects the channel pattern to the semiconductor pattern. The conductive pattern contacts a bottom edge of the channel pattern and an upper surface of the semiconductor pattern.

    摘要翻译： 一种半导体器件包括多个绝缘图案和多个栅极交替重复堆叠在基板上，沟道图案沿基本上垂直于基板顶表面的第一方向延伸穿过栅极，沟道图案 和衬底，以及沟道图案和半导体图案之间的导电图案。 导电图案将沟道图案电连接到半导体图案。 导电图案接触通道图案的底部边缘和半导体图案的上表面。

    Method for testing retention characteristics of semiconductor device having a volatile device cell and semiconductor test apparatus
    7.
    发明授权
    Method for testing retention characteristics of semiconductor device having a volatile device cell and semiconductor test apparatus 有权
    用于测试具有易失性器件单元和半导体测试装置的半导体器件的保持特性的方法

    公开(公告)号：US09099203B2

    公开(公告)日：2015-08-04

    申请号：US14060808

    申请日：2013-10-23

    申请人： Chiho Kim ,  Zhiliang Xia ,  Sung Hee Lee ,  Nara Kim ,  Dae Sin Kim

    发明人： Chiho Kim ,  Zhiliang Xia ,  Sung Hee Lee ,  Nara Kim ,  Dae Sin Kim

    IPC分类号： G11C7/00 ,  G11C29/50 ,  G11C29/56 ,  G11C11/40

    CPC分类号： G11C29/50016 ,  G11C11/40 ,  G11C29/50 ,  G11C29/56

    摘要： A test method of a semiconductor device and a semiconductor test apparatus. The test method includes providing a semiconductor device including a substrate having an active region and an isolation region, a volatile device cell including a gate insulation layer and a gate on the active region, a junction region in the active region, a capacitor connected to the junction region, and a passing gate on the isolation region, providing a first test voltage to the gate and a second test voltage greater than the first test voltage to the passing gate to deteriorate interfacial defects of the gate insulation layer, and measuring retention characteristics of the volatile device cell.

    摘要翻译： 半导体器件和半导体测试装置的测试方法。 测试方法包括提供包括具有有源区和隔离区的衬底的半导体器件，在有源区上包括栅极绝缘层和栅极的易失性器件单元，有源区中的结区，连接到 并且在隔离区域上具有通过栅极，向栅极提供第一测试电压，并且对通过栅极提供大于第一测试电压的第二测试电压，以降低栅极绝缘层的界面缺陷，并测量保留特性 易失性器件单元。

    NON-VOLATILE MEMORY DEVICES INCLUDING CHARGE STORAGE LAYERS
    10.
    发明申请
    NON-VOLATILE MEMORY DEVICES INCLUDING CHARGE STORAGE LAYERS 有权
    非易失性存储器件，包括充电储存层

    公开(公告)号：US20160240550A1

    公开(公告)日：2016-08-18

    申请号：US15043640

    申请日：2016-02-15

    申请人： JAEHUN JUNG ,  ZHILIANG XIA ,  DAEWOONG KANG ,  DAE SIN KIM ,  KWANG SOO SEOL ,  HOMIN SON ,  SEUNGHYUN LIM

    发明人： JAEHUN JUNG ,  ZHILIANG XIA ,  DAEWOONG KANG ,  DAE SIN KIM ,  KWANG SOO SEOL ,  HOMIN SON ,  SEUNGHYUN LIM

    IPC分类号： H01L27/115 ,  H01L29/792 ,  H01L29/423

    CPC分类号： H01L27/11568 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/4234 ,  H01L29/42364 ,  H01L29/512 ,  H01L29/517 ,  H01L29/518 ,  H01L29/792 ,  H01L29/7923

    摘要： A non-volatile memory device includes gate electrodes stacked on a substrate, a semiconductor pattern penetrating the gate electrodes and connected to the substrate, and a charge storage layer between the semiconductor pattern and the gate electrodes. The charge storage layer includes a first charge storage layer between the semiconductor pattern and the gate electrodes, a second charge storage layer between the first charge storage layer and the semiconductor pattern, and a third charge storage layer between the first charge storage layer and the gate electrodes. An energy band gap of the first charge storage layer is smaller than those of the second and third charge storage layers. The first charge storage layer is thicker than the second and third charge storage layers.

    摘要翻译： 非易失性存储器件包括堆叠在衬底上的栅极电极，穿过栅极并连接到衬底的半导体图案，以及半导体图案和栅电极之间的电荷存储层。 电荷存储层包括半导体图形和栅电极之间的第一电荷存储层，第一电荷存储层和半导体图案之间的第二电荷存储层，以及第一电荷存储层和栅极之间的第三电荷存储层 电极。 第一电荷存储层的能带隙比第二和第三电荷存储层的能带隙小。 第一电荷存储层比第二和第三电荷存储层厚。