公开(公告)号：US10235938B2

公开(公告)日：2019-03-19

申请号：US14904790

申请日：2014-07-03

Applicant: JOLED INC.

Inventor： Hiroshi Takahara ,  Hirofumi Nakagawa

IPC: G09G3/30 ,  G09G3/10 ,  G09G3/3258 ,  G09G3/3233 ,  G09G3/3266 ,  G09G3/3291

Abstract: A gate driver IC (i.e., gate driver circuit), when set to a first mode by a logic signal of the terminal FNC*, shifts data in the gate driver IC in synchronization with one clock cycle of a clock inputted to the terminal CLK** (clock input terminal), and outputs a selection voltage or a non-selection voltage based on a data position in the gate driver IC; and when set to a second mode by a logic signal of the terminal FNC*, shifts data in the gate driver IC in synchronization with n clock cycles (n is an integer of at least 2) of a clock inputted to the terminal CLK**, and outputs the selection voltage or the non-selection voltage based on the data position in the gate driver IC.

公开(公告)号：US10403197B2

公开(公告)日：2019-09-03

申请号：US15126082

申请日：2014-12-24

Applicant: JOLED INC.

Inventor： Hirofumi Nakagawa

IPC: G06F3/038 ,  G09G3/3225 ,  G09G3/3266 ,  G09G3/36

Abstract: A gate driver IC includes: N shift registers which generate a gate signal to be supplied to a display panel substrate, N being a natural number; (N+k) power supply terminals (PA1 to PD1, Pa1, and Pc1) for power supply from outside, k being a natural number; and (N+k) internal lines connected to the (N+k) power supply terminals, wherein N internal lines among the (N+k) internal lines connect, one-to-one, N power supply terminals among the (N+k) power supply terminals and the N shift registers, and k internal lines other than the N internal lines among the (N+k) internal lines connect, one-to-one, k power supply terminals other than the N power supply terminals among the (N+k) power supply terminals and k internal lines selected from among the N internal lines.

公开(公告)号：US10043454B2

公开(公告)日：2018-08-07

申请号：US15509674

申请日：2015-09-02

Applicant: JOLED INC.

Inventor： Hirofumi Nakagawa

IPC: G09G3/32 ,  G09G3/3258

Abstract: A source driver circuit is provided that supplies, to each of pixels arranged in a matrix, an electrical signal corresponding to a pixel signal. The source driver circuit includes a reference voltage generating unit, which includes a plurality of resistors connected in series, and a resistor, for gradation voltage generation that divides an input voltage into voltages of magnitudes. The source driver circuit also includes a gradation voltage generating circuit, which is connected between the plurality of resistors and is also connected between the plurality of resistors and the resistor for gradation voltage generation, that includes an offset-canceling amplifier. The offset-canceling amplifier alternates between an offset extraction state, in which an offset voltage of the offset-canceling amplifier is extracted, and a buffer output state, in which the offset voltage is added to the pixel signal and outputted.

公开(公告)号：US09953577B2

公开(公告)日：2018-04-24

申请号：US15101962

申请日：2014-04-10

Applicant: JOLED INC.

Inventor： Hirofumi Nakagawa ,  Hiroshi Takahara

IPC: G09G3/30 ,  G09G3/3258 ,  G09G3/3266 ,  H01L27/32 ,  G11C19/28

CPC classification number: G09G3/3258 ,  G09G3/3266 ,  G09G2310/0283 ,  G09G2310/0286 ,  G09G2310/0291 ,  G09G2310/08 ,  G11C19/28 ,  H01L27/3244

Abstract: A gate drive integrated circuit includes: clock terminals; a bidirectional buffer that is located between the clock terminals and controls the input-output direction of a clock signal; a connection mode control terminal that receives a connection mode control signal; and a pair of signal direction control terminals that receive a signal direction control signal, wherein the bidirectional buffer fixes the input-output direction of the clock signal to one direction in the case where the logic state of the connection mode control signal is a first logic state, and switches the input-output direction of the clock signal depending on the logic state of the signal direction control signal in the case where the logic state of the connection mode control signal is a second logic state different from the first logic state.

公开(公告)号：US09773452B2

公开(公告)日：2017-09-26

申请号：US14904741

申请日：2014-06-12

Applicant: JOLED INC.

Inventor： Masaru Nishimura ,  Toshiyuki Kato ,  Hirofumi Nakagawa

IPC: G09G3/30 ,  G09G3/3258 ,  H05B33/08 ,  G09G3/3266 ,  G09G3/10

CPC classification number: G09G3/3258 ,  G09G3/3266 ,  G09G2300/0871 ,  G09G2310/0286 ,  G09G2310/0291 ,  G09G2310/068 ,  G09G2320/0223 ,  G09G2320/0233 ,  G09G2320/041 ,  G09G2330/045 ,  G09G2330/08 ,  H05B33/08 ,  Y02B20/32

Abstract: An EL display apparatus includes: gate driver ICs (i. e., gate driver circuits); a plurality of pixels; gate signal lines each transmit a selection voltage for selecting a pixel from the pixels and non-selection voltage for placing a pixel in a non-selection state; and TCON. The pixels each include: a driving transistor; an EL element; a first switching transistor; and a second switching transistor. The gate driver ICs each include scanning and outputting buffer circuits which are connected to TCON to which an output signal of each of the scanning and outputting buffer circuits is inputted.