摘要:
Method and apparatus for determining occurrence of an S1 modem identification sequence is disclosed. An S1 sequence is found to exist when the sum of conjugate complex multiplication of signal sample amplitudes taken at an interval T/2 result in a negative scalar value for an arbitrary number of sequential occurrences. Complex samples taken from incoming baseband waveform at twice the modulation rate are interleaved in pairs of two with two even numbered samples and two odd numbered samples being considered separately by first performing complex multiplication followed by scalar multiplication of an output of the complex multiplication and an output of the previous complex multiplication delayed by one modulation interval T. The separate results from the sets of pairs of signal samples are summed to form a scalar whose value when consistently less than 0 indicates the presence of an S1 modem identification sequence in accordance with the CCITT S1 recommendation.
摘要:
A method, system, and computer program product for reducing power and energy consumption in a server system with multiple processor cores is disclosed. The system may include an operating system for scheduling user workloads among a processor pool. The processor pool may include active licensed processor cores and inactive unlicensed processor cores. The method and computer program product may reduce power and energy consumption by including steps and sets of instructions activating spare cores and adjusting the operating frequency of processor cores, including the newly activated spare cores to provide equivalent computing resources as the original licensed cores operating at a specified clock frequency.
摘要:
A mechanism is provided for scheduling application tasks. A scheduler receives a task that identifies a desired frequency and a desired maximum number of competing hardware threads. The scheduler determines whether a user preference designates either maximization of performance or minimization of energy consumption. Responsive to the user preference designating the performance, the scheduler determines whether there is an idle processor core in a plurality of processor cores available. Responsive to no idle processor being available, the scheduler identifies a subset of processor cores having a smallest load coefficient. From the subset of processor cores, the scheduler determines whether there is at least one processor core that matches desired parameters of the task. Responsive to at least one processor core matching the desired parameters of the task, the scheduler assigns the task to one of the at least one processor core that matches the desired parameters.
摘要:
A mechanism is provided for priority-based power capping. A power management controller identifies a set of priorities for a set of partitions of the data processing system. The power management controller determines whether a measured power of the data processing system exceeds a power cap for the data processing system. Responsive to the measured power exceeding the power cap, the power management controller sends a set of commands to a set of component actuators to adjust one or more of a set of operation parameters for a set of components associated with the set of partitions using the set of priorities. The set of component actuators adjust the one or more of the set of operational parameters associated with the set of component in order to reduce a power consumption of the data processing system.
摘要:
During manufacture, an operating range for dynamic voltage and frequency scaling can be established. A nominal operating point is identified based on a design nominal operating frequency for a computer processor. The nominal operating point comprises a nominal operating voltage identified for the design nominal operating frequency. In dependence upon the nominal operating point, an operating range of frequency and voltage over which the computer processor is to function is determined. Information specifying the nominal operating point and the operating range is stored in non-volatile storage associated with the computer processor.
摘要:
A performance control technique for a processing system that includes one or more adaptively-clocked processor cores provides improved performance/power characteristics. An outer feedback loop adjusts the power supply voltage(s) provided to the power supply voltage domain(s) powering the core(s), which may be on a per-core basis or include multiple cores per voltage domain. The outer feedback loop operates to ensure that each core is meeting specified performance, while the cores also include an inner feedback loop that adjusts their processor clock or other performance control mechanism to maximize performance under present operating conditions and within a margin of safety. The performance of each core is measured and compared to a target performance. If the target performance is not met for each core in a voltage domain, the voltage is raised for the voltage domain until all cores meet the target performance.
摘要:
A mechanism is provided for dynamically power capping one or more units. A power capping mechanism sets a counter value corresponding to an initial energy budget assigned to a unit for a given interval. Responsive to the unit receiving an operation to perform during the given interval, the power capping mechanism decrements the counter value by a decrement value. Responsive to the given interval expiring, the power capping mechanism sends the counter value to a power control loop in the data processing system, receives a new energy budget from the power control loop, and resets the counter value to a value corresponding to the new energy budget assigned to the unit for a next interval.
摘要:
A mechanism is provided for priority-based power capping. A power management controller identifies a set of priorities for a set of partitions of the data processing system. The power management controller determines whether a measured power of the data processing system exceeds a power cap for the data processing system. Responsive to the measured power exceeding the power cap, the power management controller sends a set of commands to a set of component actuators to adjust one or more of a set of operation parameters for a set of components associated with the set of partitions using the set of priorities. The set of component actuators adjust the one or more of the set of operational parameters associated with the set of component in order to reduce a power consumption of the data processing system.
摘要:
A mechanism is provided for oversubscribing branch circuits. An active energy management mechanism determines a cumulative wattage rating using power consumption information for a powered element, the power consumption information is for a primary and a redundant portion of the powered element. The active energy management mechanism determines a power reduction power cap to be used by the powered element in the event of a loss of either a primary or a redundant power source supplied to the powered element using the cumulative wattage rating, a branch circuit rating, and a circuit breaker rating for the powered element. The active energy management mechanism sends the power reduction power cap to the powered element in order that the powered element reduces power to the power reduction power cap in the event of the loss of either the primary power source or the redundant power source supplied to the powered element.
摘要:
Methods and products for managing power consumption of a computer and computers for which power consumption is managed. The computer includes the computer including a computer processor and embodiments of the present invention include providing, by an in-band power manger to an out-of-band power manager, a proposed performance state (‘p-state’) for the computer processor; determining, by the out-of-band power manager, in dependence upon a power setpoint and currently-measured operating metrics of the computer processor, whether to approve the proposed p-state; and if the out-of-band power manager approves the proposed p-state, setting operating parameters of the computer processor according to the approved p-state.