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41 条记录 (耗时 0.024 秒)

    Method and apparatus for programmable sampling clock edge selection
    2.
    发明授权
    Method and apparatus for programmable sampling clock edge selection 有权
    用于可编程采样时钟沿选择的方法和装置

    公开(公告)号：US07275171B2

    公开(公告)日：2007-09-25

    申请号：US10443297

    申请日：2003-05-22

    申请人： Jade M. Kizer ,  Benedict C. Lau ,  Bradley A. May

    发明人： Jade M. Kizer ,  Benedict C. Lau ,  Bradley A. May

    IPC分类号： H04L7/00

    CPC分类号： G06F1/12

    摘要： A method and apparatus for transferring data across a clock domain boundary is described. In one embodiment, a fixed relationship between a faster clock and a slower clock is maintained in the process of phase alignment to allow great flexibility in allowable combinations of slower clock and faster clock frequencies. In one embodiment, an encoded edge select word is generated once at system initialization and used thereafter to select edges of the faster clock on which to sample data that comes from the clock domain of the slower clock. The value of the encoded edge select word is based, in part, on the fixed relationship between the faster clock and the slower clock.

    摘要翻译： 描述了用于在时钟域边界上传送数据的方法和装置。 在一个实施例中，在相位对准的过程中保持较快时钟和较慢时钟之间的固定关系，以允许较慢时钟和较快时钟频率的可允许组合中的较大灵活性。 在一个实施例中，编码边缘选择字在系统初始化时产生一次，并且此后使用其选择在其上采样来自较慢时钟的时钟域的数据的较快时钟的边沿。 编码边缘选择字的值部分地基于较快时钟和较慢时钟之间的固定关系。

    Phase jumping locked loop circuit
    6.
    发明授权
    Phase jumping locked loop circuit 有权
    相跳锁定回路电路

    公开(公告)号：US07135903B2

    公开(公告)日：2006-11-14

    申请号：US10374251

    申请日：2003-02-25

    申请人： Jade M. Kizer ,  Benedict C. Lau ,  Roxanne T. Vu ,  Huy M. Nguyen ,  Leung Yu ,  Adam Chuen-Huei Chou

    发明人： Jade M. Kizer ,  Benedict C. Lau ,  Roxanne T. Vu ,  Huy M. Nguyen ,  Leung Yu ,  Adam Chuen-Huei Chou

    IPC分类号： H03L7/06

    CPC分类号： H03L7/0805 ,  G06F1/10 ,  H03L7/07 ,  H03L7/0814

    摘要： A phase-jumping locked loop circuit. The locked loop circuit includes a plurality of differential amplifiers and a biasing circuit switchably coupled to each of the differential amplifiers. Each of the differential amplifiers has inputs to receive a respective pair of clock signals and outputs coupled to a common pair of output signal lines. The biasing circuit comprising a first plurality of biasing transistors coupled in parallel with one another and in series with a first set of the differential amplifiers, and a second plurality of biasing transistors coupled in parallel with one another and in series with a second set of the differential amplifiers.

    摘要翻译： 一个跳相锁定环路。 锁定环电路包括多个差分放大器和可切换地耦合到每个差分放大器的偏置电路。 每个差分放大器具有输入以接收耦合到公共输出信号线对的相应的一对时钟信号和输出。 偏置电路包括彼此并联并与第一组差分放大器串联耦合的第一多个偏置晶体管，以及第二组多个偏置晶体管，其彼此并联耦合并与第二组 差分放大器。

    Phase synchronization for wide area integrated circuits
    9.
    发明授权
    Phase synchronization for wide area integrated circuits 有权
    广域集成电路的相位同步

    公开(公告)号：US07932755B2

    公开(公告)日：2011-04-26

    申请号：US11620309

    申请日：2007-01-05

    申请人： Huy M. Nguyen ,  Benedict C. Lau ,  Leung Yu ,  Jade M. Kizer

    发明人： Huy M. Nguyen ,  Benedict C. Lau ,  Leung Yu ,  Jade M. Kizer

    IPC分类号： H03L7/06

    CPC分类号： G06F1/10 ,  G06F1/12 ,  H03L7/00

    摘要： A circuit and method for synchronized clocking of components such as registers. Registers are clocked by individual component clock signals having the same frequency but potentially different phases due to differing propagation delays. Separate component clock signals are received by registers are brought into phase by evaluating the phases of the component clock signals at the registers, and synchronizing the component clock signal of each register to that of the previous register in a sequence.

    摘要翻译： 用于同步计时器件的电路和方法，例如寄存器。 由于不同的传播延迟，寄存器由具有相同频率但潜在不同相位的各个组件时钟信号计时。 通过对寄存器中的分量时钟信号的相位进行评估，使寄存器接收到的单独的分量时钟信号变为相位，并且将序列中的每个寄存器的分量时钟信号与先前寄存器的分量时钟信号同步。