公开(公告)号：US20090296486A1

公开(公告)日：2009-12-03

申请号：US12382351

申请日：2009-03-13

申请人： Jae Hong Kim ,  Kyoung Lae Cho ,  Yong June Kim ,  Dong Hyuk Chae

发明人： Jae Hong Kim ,  Kyoung Lae Cho ,  Yong June Kim ,  Dong Hyuk Chae

IPC分类号： G11C16/06

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C2211/5621

摘要： Memory devices and/or memory programming methods are provided. A memory device may include: a memory cell array including a plurality of memory cells; a programming unit configured to apply a plurality of pulses corresponding to a program voltage to a gate terminal of each of the plurality of memory cells, and to apply a program condition voltage to a bit line connected with a memory cell having a threshold voltage lower than a verification voltage from among the plurality of memory cells; and a control unit configured to increase the program voltage during a first time interval by a first increment for each pulse, and to increase the program voltage during a second time interval by a second increment for each pulse. Through this, it may be possible to reduce a width of a distribution of threshold voltages of a memory cell.

摘要翻译： 提供存储器件和/或存储器编程方法。 存储器件可以包括：包括多个存储器单元的存储单元阵列; 编程单元，被配置为将与编程电压相对应的多个脉冲施加到所述多个存储单元中的每一个的栅极端子，并且将编程状态电压施加到与具有低于阈值电压的阈值电压的存储单元连接的位线 来自所述多个存储单元中的验证电压; 以及控制单元，被配置为在每个脉冲的第一时间间隔期间增加编程电压的第一增量，并且在第二时间间隔期间增加每个脉冲的第二增量的编程电压。 由此，可以减小存储单元的阈值电压分布的宽度。

公开(公告)号：US08059467B2

公开(公告)日：2011-11-15

申请号：US12382351

申请日：2009-03-13

申请人： Jae Hong Kim ,  Kyoung Lae Cho ,  Yong June Kim ,  Dong Hyuk Chae

发明人： Jae Hong Kim ,  Kyoung Lae Cho ,  Yong June Kim ,  Dong Hyuk Chae

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C2211/5621

摘要： Memory devices and/or memory programming methods are provided. A memory device may include: a memory cell array including a plurality of memory cells; a programming unit configured to apply a plurality of pulses corresponding to a program voltage to a gate terminal of each of the plurality of memory cells, and to apply a program condition voltage to a bit line connected with a memory cell having a threshold voltage lower than a verification voltage from among the plurality of memory cells; and a control unit configured to increase the program voltage during a first time interval by a first increment for each pulse, and to increase the program voltage during a second time interval by a second increment for each pulse. Through this, it may be possible to reduce a width of a distribution of threshold voltages of a memory cell.

摘要翻译： 提供存储器件和/或存储器编程方法。 存储器件可以包括：包括多个存储器单元的存储单元阵列; 编程单元，被配置为将与编程电压相对应的多个脉冲施加到所述多个存储单元中的每一个的栅极端子，并且将编程状态电压施加到与具有低于阈值电压的阈值电压的存储单元连接的位线 来自所述多个存储单元中的验证电压; 以及控制单元，被配置为在每个脉冲的第一时间间隔期间增加编程电压的第一增量，并且在第二时间间隔期间增加每个脉冲的第二增量的编程电压。 由此，可以减小存储单元的阈值电压分布的宽度。

公开(公告)号：US07924624B2

公开(公告)日：2011-04-12

申请号：US12385705

申请日：2009-04-16

申请人： Jae Hong Kim ,  Kyoung Lae Cho ,  Dong Hyuk Chae ,  Yong June Kim

发明人： Jae Hong Kim ,  Kyoung Lae Cho ,  Dong Hyuk Chae ,  Yong June Kim

IPC分类号： G11C16/06

CPC分类号： G11C16/3454 ,  G11C11/5628 ,  G11C2211/5621

摘要： Provided are memory devices and memory programming methods. A memory device may include: a multi-bit cell array that includes a plurality of memory cells; a controller that extracts state information of each of the memory cells, divides the plurality of memory cells into a first group and a second group, assigns a first verify voltage to memory cells of the first group and assigns a second verify voltage to memory cells of the second group; and a programming unit that changes a threshold voltage of each memory cell of the first group until the threshold voltage of each memory cell of the first group is greater than or equal to the first verify voltage, and changes a threshold voltage of each memory cell of the second group until the threshold voltage of each memory cell of the second group is greater than or equal to the second verify voltage.

摘要翻译： 提供的是存储器件和存储器编程方法。 存储器设备可以包括：包括多个存储器单元的多位单元阵列; 提取每个存储单元的状态信息的控制器，将多个存储器单元划分成第一组和第二组，将第一验证电压分配给第一组的存储单元，并将第二验证电压分配给存储单元 第二组 以及编程单元，其改变第一组的每个存储单元的阈值电压，直到第一组的每个存储单元的阈值电压大于或等于第一验证电压，并且改变每个存储单元的阈值电压 直到第二组的每个存储单元的阈值电压大于或等于第二验证电压。

公开(公告)号：US20090296466A1

公开(公告)日：2009-12-03

申请号：US12385705

申请日：2009-04-16

申请人： Jae Hong Kim ,  Kyoung Lae Cho ,  Dong Hyuk Chae ,  Yong June Kim

发明人： Jae Hong Kim ,  Kyoung Lae Cho ,  Dong Hyuk Chae ,  Yong June Kim

IPC分类号： G11C16/02 ,  G11C16/06

CPC分类号： G11C16/3454 ,  G11C11/5628 ,  G11C2211/5621

摘要： Provided are memory devices and memory programming methods. A memory device may include: a multi-bit cell array that includes a plurality of memory cells; a controller that extracts state information of each of the memory cells, divides the plurality of memory cells into a first group and a second group, assigns a first verify voltage to memory cells of the first group and assigns a second verify voltage to memory cells of the second group; and a programming unit that changes a threshold voltage of each memory cell of the first group until the threshold voltage of each memory cell of the first group is greater than or equal to the first verify voltage, and changes a threshold voltage of each memory cell of the second group until the threshold voltage of each memory cell of the second group is greater than or equal to the second verify voltage.

摘要翻译： 提供的是存储器件和存储器编程方法。 存储器设备可以包括：包括多个存储器单元的多位单元阵列; 提取每个存储单元的状态信息的控制器，将多个存储单元划分为第一组和第二组，将第一验证电压分配给第一组的存储单元，并将第二验证电压分配给存储单元 第二组 以及编程单元，其改变第一组的每个存储单元的阈值电压，直到第一组的每个存储单元的阈值电压大于或等于第一验证电压，并且改变每个存储单元的阈值电压 直到第二组的每个存储单元的阈值电压大于或等于第二验证电压。

公开(公告)号：US07821828B2

公开(公告)日：2010-10-26

申请号：US12219104

申请日：2008-07-16

申请人： Seung-Hwan Song ,  Jun Jin Kong ,  Jae Hong Kim ,  Young Hwan Lee ,  Dong Hyuk Chae ,  Tae Hun Kim ,  Kyoung Lae Cho

发明人： Seung-Hwan Song ,  Jun Jin Kong ,  Jae Hong Kim ,  Young Hwan Lee ,  Dong Hyuk Chae ,  Tae Hun Kim ,  Kyoung Lae Cho

IPC分类号： G11C16/04

CPC分类号： G11C16/3418 ,  G11C7/04 ,  G11C11/5621 ,  G11C16/3427 ,  G11C16/349 ,  G11C29/00

摘要： A memory device and a memory device heat treatment method are provided. The memory device may include: a non-volatile memory device; one or more heating devices configured to contact with the non-volatile memory device and heat the non-volatile memory device; and a controller configured to control an operation of the one or more heating devices based on operational information of the non-volatile memory device. Through this, it may be possible to improve an available period of the non-volatile memory device.

摘要翻译： 提供了一种存储器件和存储器件热处理方法。 存储器件可以包括：非易失性存储器件; 配置成与所述非易失性存储器件接触并加热所述非易失性存储器件的一个或多个加热器件; 以及控制器，被配置为基于所述非易失性存储器件的操作信息来控制所述一个或多个加热装置的操作。 由此，可以改善非易失性存储器件的可用周期。

公开(公告)号：US08239747B2

公开(公告)日：2012-08-07

申请号：US12216744

申请日：2008-07-10

申请人： Kyoung Lae Cho ,  Jae Hong Kim ,  Yoon Dong Park ,  Jun Jin Kong ,  Dong Hyuk Chae

发明人： Kyoung Lae Cho ,  Jae Hong Kim ,  Yoon Dong Park ,  Jun Jin Kong ,  Dong Hyuk Chae

IPC分类号： G06F11/00

CPC分类号： G06F11/1072 ,  H03M13/09 ,  H03M13/15 ,  H03M13/1515 ,  H03M13/152

摘要： Example embodiments may provide a memory device and memory data reading method. The memory device according to example embodiments may include a multi-bit cell array, an error detector which may read a first data page from a memory page in the multi-bit cell array and may detect an error-bit of the first data page, and an estimator which may identify a multi-bit cell where the error-bit is stored and may estimate data stored in the identified multi-bit cell among data of a second data page. Therefore, the memory device and memory data reading method may have an effect of reducing an error when reading data stored in the multi-bit cell and monitoring a state of the multi-bit cell without additional overhead.

摘要翻译： 示例性实施例可以提供存储器件和存储器数据读取方法。 根据示例实施例的存储器件可以包括多位单元阵列，错误检测器，其可以从多位单元阵列中的存储器页读取第一数据页，并且可以检测第一数据页的错误位， 以及估计器，其可以识别存储错误位的多位单元，并且可以估计存储在所识别的多位单元中的数据在第二数据页的数据中。 因此，存储器件和存储器数据读取方法可以具有当读取存储在多位单元中的数据并且监视多位单元的状态而没有额外开销时减小误差的效果。

公开(公告)号：US07929346B2

公开(公告)日：2011-04-19

申请号：US12216745

申请日：2008-07-10

申请人： Dong Hun Yu ,  Kyoung Lae Cho ,  Dong Hyuk Chae ,  Jun Jin Kong ,  Jae Hong Kim ,  Seung-Hwan Song

发明人： Dong Hun Yu ,  Kyoung Lae Cho ,  Dong Hyuk Chae ,  Jun Jin Kong ,  Jae Hong Kim ,  Seung-Hwan Song

IPC分类号： G11C16/06 ,  G11C16/34 ,  G11C16/26

CPC分类号： G11C7/1006 ,  G11C7/14 ,  G11C11/5642 ,  G11C29/00 ,  G11C29/028 ,  G11C29/42 ,  G11C29/50 ,  G11C2211/5634

摘要： Example embodiments may relate to a method and an apparatus for reading data stored in a memory, for example, providing a method and an apparatus for controlling a reference voltage based on an error of the stored data. Example embodiments may provide a memory data detecting apparatus including a first voltage comparator to compare a threshold voltage of a memory cell with a first reference voltage, a first data determiner to determine a value of at least one data bit stored in the memory cell according to a result of the comparison, an error verifier to verify whether an error occurs in the determined value, a reference voltage determiner to determine a second reference voltage that is lower than the first reference voltage based on a result of the verification, and a second data determiner to re-determine the value of the data based on the determined second reference voltage.

摘要翻译： 示例性实施例可以涉及用于读取存储在存储器中的数据的方法和装置，例如提供一种基于存储的数据的错误来控制参考电压的方法和装置。 示例性实施例可以提供一种存储器数据检测装置，其包括用于将存储器单元的阈值电压与第一参考电压进行比较的第一电压比较器，第一数据确定器，用于根据存储器单元存储的至少一个数据位的值，根据 比较结果，用于验证所确定的值是否发生错误验证器，基于验证结果确定低于第一参考电压的第二参考电压的参考电压确定器，以及第二数据 确定器，以基于所确定的第二参考电压重新确定数据的值。

公开(公告)号：US20090207671A1

公开(公告)日：2009-08-20

申请号：US12216745

申请日：2008-07-10

申请人： Dong Hun Yu ,  Kyoung Lae Cho ,  Dong Hyuk Chae ,  Jun Jin Kong ,  Jae Hong Kim ,  Seung-Hwan Song

发明人： Dong Hun Yu ,  Kyoung Lae Cho ,  Dong Hyuk Chae ,  Jun Jin Kong ,  Jae Hong Kim ,  Seung-Hwan Song

IPC分类号： G11C7/00 ,  G11C29/04

CPC分类号： G11C7/1006 ,  G11C7/14 ,  G11C11/5642 ,  G11C29/00 ,  G11C29/028 ,  G11C29/42 ,  G11C29/50 ,  G11C2211/5634

摘要： Example embodiments may relate to a method and an apparatus for reading data stored in a memory, for example, providing a method and an apparatus for controlling a reference voltage based on an error of the stored data. Example embodiments may provide a memory data detecting apparatus including a first voltage comparator to compare a threshold voltage of a memory cell with a first reference voltage, a first data determiner to determine a value of at least one data bit stored in the memory cell according to a result of the comparison, an error verifier to verify whether an error occurs in the determined value, a reference voltage determiner to determine a second reference voltage that is lower than the first reference voltage based on a result of the verification, and a second data determiner to re-determine the value of the data based on the determined second reference voltage.

摘要翻译： 示例性实施例可以涉及用于读取存储在存储器中的数据的方法和装置，例如提供一种基于存储的数据的错误来控制参考电压的方法和装置。 示例性实施例可以提供一种存储器数据检测装置，其包括用于将存储器单元的阈值电压与第一参考电压进行比较的第一电压比较器，第一数据确定器，用于根据存储器单元存储的至少一个数据位的值，根据 比较结果，用于验证所确定的值是否发生错误验证器，基于验证结果确定低于第一参考电压的第二参考电压的参考电压确定器，以及第二数据 确定器，以基于所确定的第二参考电压重新确定数据的值。

公开(公告)号：US20090201729A1

公开(公告)日：2009-08-13

申请号：US12219104

申请日：2008-07-16

申请人： Seung-Hwan Song ,  Jun Jin Kong ,  Jae Hong Kim ,  Young Hwan Lee ,  Dong Hyuk Chae ,  Tae Hun Kim ,  Kyoung Lae Cho

发明人： Seung-Hwan Song ,  Jun Jin Kong ,  Jae Hong Kim ,  Young Hwan Lee ,  Dong Hyuk Chae ,  Tae Hun Kim ,  Kyoung Lae Cho

IPC分类号： G11C16/04

CPC分类号： G11C16/3418 ,  G11C7/04 ,  G11C11/5621 ,  G11C16/3427 ,  G11C16/349 ,  G11C29/00

摘要： A memory device and a memory device heat treatment method are provided. The memory device may include: a non-volatile memory device; one or more heating devices configured to contact with the non-volatile memory device and heat the non-volatile memory device; and a controller configured to control an operation of the one or more heating devices based on operational information of the non-volatile memory device. Through this, it may be possible to improve an available period of the non-volatile memory device.

摘要翻译： 提供了一种存储器件和存储器件热处理方法。 存储器件可以包括：非易失性存储器件; 配置成与所述非易失性存储器件接触并加热所述非易失性存储器件的一个或多个加热器件; 以及控制器，被配置为基于所述非易失性存储器件的操作信息来控制所述一个或多个加热装置的操作。 由此，可以改善非易失性存储器件的可用周期。

公开(公告)号：US20090210776A1

公开(公告)日：2009-08-20

申请号：US12216744

申请日：2008-07-10

申请人： Kyoung Lae Cho ,  Jae Hong Kim ,  Yoon Dong Park ,  Jun Jin Kong ,  Dong Hyuk Chae

发明人： Kyoung Lae Cho ,  Jae Hong Kim ,  Yoon Dong Park ,  Jun Jin Kong ,  Dong Hyuk Chae

IPC分类号： H03M13/09 ,  G06F11/10

CPC分类号： G06F11/1072 ,  H03M13/09 ,  H03M13/15 ,  H03M13/1515 ,  H03M13/152

摘要： Example embodiments may provide a memory device and memory data reading method. The memory device according to example embodiments may include a multi-bit cell array, an error detector which may read a first data page from a memory page in the multi-bit cell array and may detect an error-bit of the first data page, and an estimator which may identify a multi-bit cell where the error-bit is stored and may estimate data stored in the identified multi-bit cell among data of a second data page. Therefore, the memory device and memory data reading method may have an effect of reducing an error when reading data stored in the multi-bit cell and monitoring a state of the multi-bit cell without additional overhead.

摘要翻译： 示例性实施例可以提供存储器件和存储器数据读取方法。 根据示例实施例的存储器件可以包括多位单元阵列，错误检测器，其可以从多位单元阵列中的存储器页读取第一数据页，并且可以检测第一数据页的错误位， 以及估计器，其可以识别存储错误位的多位单元，并且可以估计存储在所识别的多位单元中的数据在第二数据页的数据中。 因此，存储器件和存储器数据读取方法可以具有当读取存储在多位单元中的数据并且监视多位单元的状态而没有额外开销时减小误差的效果。