公开(公告)号：US20050151276A1

公开(公告)日：2005-07-14

申请号：US11032725

申请日：2005-01-11

申请人： Jae-Hoon Jang ,  Soon-Moon Jung ,  Kun-Ho Kwak ,  Byung-Jun Hwang

发明人： Jae-Hoon Jang ,  Soon-Moon Jung ,  Kun-Ho Kwak ,  Byung-Jun Hwang

IPC分类号： H01L21/768 ,  H01L21/20 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8244 ,  H01L21/84 ,  H01L27/01 ,  H01L27/10 ,  H01L27/11 ,  H01L27/12 ,  H01L29/786

CPC分类号： H01L27/11 ,  H01L27/1108 ,  Y10S257/903

摘要： A static random-access memory (SRAM) device may include a bulk MOS transistor on a semiconductor substrate having a source/drain region therein, an insulating layer on the bulk MOS transistor, and a thin-film transistor having a source/drain region therein on the insulating layer above the bulk MOS transistor. The device may further include a multi-layer plug between the bulk MOS transistor and the thin-film transistor. The multi-layer plug may include a semiconductor plug directly on the source/drain region of the bulk MOS transistor and extending through at least a portion of the insulating layer, and a metal plug directly on the source/drain region of the thin-film transistor and the semiconductor plug and extending through at least a portion of the insulating layer. Related methods are also discussed.

摘要翻译： 静态随机存取存储器（SRAM）器件可以包括在其中具有源极/漏极区域的半导体衬底上的体MOS晶体管，体MOS晶体管上的绝缘层，以及在其中具有源极/漏极区域的薄膜晶体管 在体MOS晶体管上方的绝缘层上。 器件还可以包括在体MOS晶体管和薄膜晶体管之间的多层插头。 多层插头可以包括直接在体MOS晶体管的源极/漏极区域上并延伸穿过绝缘层的至少一部分的半导体插头，以及直接在薄膜的源极/漏极区域上的金属插塞 晶体管和半导体插头并延伸穿过绝缘层的至少一部分。 还讨论了相关方法。

公开(公告)号：US20050179061A1

公开(公告)日：2005-08-18

申请号：US11033432

申请日：2005-01-11

申请人： Jae-Hoon Jang ,  Soon-Moon Jung ,  Kun-Ho Kwak ,  Byung-Jun Hwang

发明人： Jae-Hoon Jang ,  Soon-Moon Jung ,  Kun-Ho Kwak ,  Byung-Jun Hwang

IPC分类号： H01L29/417 ,  H01L21/768 ,  H01L21/77 ,  H01L21/8244 ,  H01L21/84 ,  H01L27/06 ,  H01L27/11 ,  H01L27/12 ,  H01L29/41 ,  H01L29/786 ,  H01L27/10

CPC分类号： H01L27/1214 ,  H01L27/0688 ,  H01L27/11 ,  H01L27/1108

摘要： Semiconductor integrated circuits that include thin film transistors (TFTs) and methods of fabricating such semiconductor integrated circuits are provided. The semiconductor integrated circuits may include a bulk transistor formed at a semiconductor substrate and a first interlayer insulating layer on the bulk transistor. A lower TFT may be on the first interlayer insulating layer, and a second interlayer insulating layer may be on the lower TFT. An upper TFT may be on the second interlayer insulating layer, and a third interlayer insulating layer may be on the upper TFT. A first impurity region of the bulk transistor, a first impurity region of the lower TFT, and a first impurity region of the upper TFT may be electrically connected to one another through a node plug that penetrates the first, second and third interlayer insulating layers.

摘要翻译： 提供包括薄膜晶体管（TFT）的半导体集成电路和制造这种半导体集成电路的方法。 半导体集成电路可以包括形成在半导体衬底上的体晶体管和体晶体管上的第一层间绝缘层。 下部TFT可以在第一层间绝缘层上，第二层间绝缘层可以在下部TFT上。 上层TFT可以在第二层间绝缘层上，第三层间绝缘层可以在上部TFT上。 本体晶体管的第一杂质区，下TFT的第一杂质区和上TFT的第一杂质区可以通过穿透第一，第二和第三层间绝缘层的节点插塞彼此电连接。

公开(公告)号：US07479673B2

公开(公告)日：2009-01-20

申请号：US11033432

申请日：2005-01-11

申请人： Jae-Hoon Jang ,  Soon-Moon Jung ,  Kun-Ho Kwak ,  Byung-Jun Hwang

发明人： Jae-Hoon Jang ,  Soon-Moon Jung ,  Kun-Ho Kwak ,  Byung-Jun Hwang

IPC分类号： H01L27/02

CPC分类号： H01L27/1214 ,  H01L27/0688 ,  H01L27/11 ,  H01L27/1108

摘要： Semiconductor integrated circuits that include thin film transistors (TFTs) and methods of fabricating such semiconductor integrated circuits are provided. The semiconductor integrated circuits may include a bulk transistor formed at a semiconductor substrate and a first interlayer insulating layer on the bulk transistor. A lower TFT may be on the first interlayer insulating layer, and a second interlayer insulating layer may be on the lower TFT. An upper TFT may be on the second interlayer insulating layer, and a third interlayer insulating layer may be on the upper TFT. A first impurity region of the bulk transistor, a first impurity region of the lower TFT, and a first impurity region of the upper TFT may be electrically connected to one another through a node plug that penetrates the first, second and third interlayer insulating layers.

摘要翻译： 提供包括薄膜晶体管（TFT）的半导体集成电路和制造这种半导体集成电路的方法。 半导体集成电路可以包括形成在半导体衬底上的体晶体管和体晶体管上的第一层间绝缘层。 下部TFT可以在第一层间绝缘层上，第二层间绝缘层可以在下部TFT上。 上层TFT可以在第二层间绝缘层上，第三层间绝缘层可以在上部TFT上。 本体晶体管的第一杂质区，下TFT的第一杂质区和上TFT的第一杂质区可以通过穿透第一，第二和第三层间绝缘层的节点插塞彼此电连接。

公开(公告)号：US20080023728A1

公开(公告)日：2008-01-31

申请号：US11868648

申请日：2007-10-08

申请人： Jae-Hoon Jang ,  Soon-Moon Jung ,  Kun-Ho Kwak ,  Byung-Jun Hwang

发明人： Jae-Hoon Jang ,  Soon-Moon Jung ,  Kun-Ho Kwak ,  Byung-Jun Hwang

IPC分类号： H01L27/10

CPC分类号： H01L27/1214 ,  H01L23/481 ,  H01L27/0688 ,  H01L27/11 ,  H01L27/1108

摘要： Semiconductor integrated circuits that include thin film transistors (TFTs) and methods of fabricating such semiconductor integrated circuits are provided. The semiconductor integrated circuits may include a bulk transistor formed at a semiconductor substrate and a first interlayer insulating layer on the bulk transistor. A lower TFT may be on the first interlayer insulating layer, and a second interlayer insulating layer may be on the lower TFT. An upper TFT may be on the second interlayer insulating layer, and a third interlayer insulating layer may be on the upper TFT. A first impurity region of the bulk transistor, a first impurity region of the lower TFT, and a first impurity region of the upper TFT may be electrically connected to one another through a node plug that penetrates the first, second and third interlayer insulating layers.

摘要翻译： 提供包括薄膜晶体管（TFT）的半导体集成电路和制造这种半导体集成电路的方法。 半导体集成电路可以包括形成在半导体衬底上的体晶体管和体晶体管上的第一层间绝缘层。 下部TFT可以在第一层间绝缘层上，第二层间绝缘层可以在下部TFT上。 上层TFT可以在第二层间绝缘层上，第三层间绝缘层可以在上部TFT上。 本体晶体管的第一杂质区，下TFT的第一杂质区和上TFT的第一杂质区可以通过穿透第一，第二和第三层间绝缘层的节点插塞彼此电连接。

公开(公告)号：US07247528B2

公开(公告)日：2007-07-24

申请号：US11065750

申请日：2005-02-24

申请人： Kun-Ho Kwak ,  Jae-Hoon Jang ,  Soon-Moon Jung ,  Won-Seok Cho ,  Hoon Lim ,  Sung-Jin Kim ,  Byung-Jun Hwang ,  Jong-Hyuk Kim

发明人： Kun-Ho Kwak ,  Jae-Hoon Jang ,  Soon-Moon Jung ,  Won-Seok Cho ,  Hoon Lim ,  Sung-Jin Kim ,  Byung-Jun Hwang ,  Jong-Hyuk Kim

IPC分类号： H01L21/00

CPC分类号： H01L27/1108 ,  H01L27/11

摘要： Methods of fabricating a semiconductor integrated circuit having thin film transistors using an SEG technique are provided. The methods include forming an inter-layer insulating layer on a single-crystalline semiconductor substrate. A single-crystalline semiconductor plug extends through the inter-layer insulating layer, and a single-crystalline epitaxial semiconductor pattern is in contact with the single-crystalline semiconductor plug on the inter-layer insulating layer. The single-crystalline epitaxial semiconductor pattern is at least partially planarized to form a semiconductor body layer on the inter-layer insulating layer, and the semiconductor body layer is patterned to form a semiconductor body. As a result, the semiconductor body includes at least a portion of the single-crystalline epitaxial semiconductor pattern. Thus, the semiconductor body has an excellent single-crystalline structure. Semiconductor integrated circuits fabricated using the methods are also provided.

摘要翻译： 提供了使用SEG技术制造具有薄膜晶体管的半导体集成电路的方法。 所述方法包括在单晶半导体衬底上形成层间绝缘层。 单晶半导体插件延伸穿过层间绝缘层，并且单晶外延半导体图案与层间绝缘层上的单晶半导体插头接触。 单晶外延半导体图案至少部分地平坦化以在层间绝缘层上形成半导体本体层，并且对半导体本体层进行图案化以形成半导体本体。 结果，半导体本体包括单晶外延半导体图案的至少一部分。 因此，半导体本体具有优异的单晶结构。 还提供了使用这些方法制造的半导体集成电路。

公开(公告)号：US20050221544A1

公开(公告)日：2005-10-06

申请号：US11098648

申请日：2005-04-04

申请人： Kun-Ho Kwak ,  Sung-Jin Kim ,  Soon-Moon Jung ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Hoon Lim ,  Jong-Hyuk Kim ,  Myang-Sik Han ,  Byung-Jun Hwang

发明人： Kun-Ho Kwak ,  Sung-Jin Kim ,  Soon-Moon Jung ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Hoon Lim ,  Jong-Hyuk Kim ,  Myang-Sik Han ,  Byung-Jun Hwang

IPC分类号： H01L21/00 ,  H01L21/8244 ,  H01L21/84 ,  H01L27/06 ,  H01L27/11 ,  H01L27/12 ,  H01L29/15 ,  H01L29/786 ,  H01L31/0312

CPC分类号： H01L27/1108 ,  H01L27/0688 ,  H01L27/11 ,  H01L29/78603

摘要： Methods of fabricating semiconductor devices are provided. An interlayer insulating layer is provided on a single crystalline semiconductor substrate. A single crystalline semiconductor plug is provided that extends through the interlayer insulating layer and a molding layer pattern is provided on the semiconductor substrate and the single crystalline semiconductor plug. The molding layer pattern defines an opening therein that at least partially exposes a portion of the single crystalline semiconductor plug. A single crystalline semiconductor epitaxial pattern is provided on the exposed portion of single crystalline semiconductor plug using a selective epitaxial growth technique that uses the exposed portion of the single crystalline semiconductor plug as a seed layer. A single crystalline semiconductor region is provided in the opening. The single crystalline semiconductor region includes at least a portion of the single crystalline semiconductor epitaxial pattern.

摘要翻译： 提供制造半导体器件的方法。 层间绝缘层设置在单晶半导体衬底上。 提供延伸穿过层间绝缘层的单晶半导体插头，并且在半导体衬底和单晶半导体插头上设置成型层图案。 模制层图案限定其中的开口，其至少部分地暴露单晶半导体插塞的一部分。 使用选择性外延生长技术在单晶半导体插塞的暴露部分上提供单晶半导体外延图案，其使用单晶半导体插塞的暴露部分作为籽晶层。 在开口中设置单晶半导体区域。 单晶半导体区域包括单晶半导体外延图案的至少一部分。

公开(公告)号：US07521715B2

公开(公告)日：2009-04-21

申请号：US11032725

申请日：2005-01-11

申请人： Jae-Hoon Jang ,  Soon-Moon Jung ,  Kun-Ho Kwak ,  Byung-Jun Hwang

发明人： Jae-Hoon Jang ,  Soon-Moon Jung ,  Kun-Ho Kwak ,  Byung-Jun Hwang

IPC分类号： H01L27/108

CPC分类号： H01L27/11 ,  H01L27/1108 ,  Y10S257/903

摘要： A static random-access memory (SRAM) device may include a bulk MOS transistor on a semiconductor substrate having a source/drain region therein, an insulating layer on the bulk MOS transistor, and a thin-film transistor having a source/drain region therein on the insulating layer above the bulk MOS transistor. The device may further include a multi-layer plug between the bulk MOS transistor and the thin-film transistor. The multi-layer plug may include a semiconductor plug directly on the source/drain region of the bulk MOS transistor and extending through at least a portion of the insulating layer, and a metal plug directly on the source/drain region of the thin-film transistor and the semiconductor plug and extending through at least a portion of the insulating layer. Related methods are also discussed.

摘要翻译： 静态随机存取存储器（SRAM）器件可以包括在其中具有源极/漏极区域的半导体衬底上的体MOS晶体管，体MOS晶体管上的绝缘层，以及在其中具有源极/漏极区域的薄膜晶体管 在体MOS晶体管上方的绝缘层上。 器件还可以包括在体MOS晶体管和薄膜晶体管之间的多层插头。 多层插头可以包括直接在体MOS晶体管的源极/漏极区域上并延伸穿过绝缘层的至少一部分的半导体插头，以及直接在薄膜的源极/漏极区域上的金属插塞 晶体管和半导体插头并延伸穿过绝缘层的至少一部分。 还讨论了相关方法。

公开(公告)号：US07312110B2

公开(公告)日：2007-12-25

申请号：US11098648

申请日：2005-04-04

申请人： Kun-Ho Kwak ,  Sung-Jin Kim ,  Soon-Moon Jung ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Hoon Lim ,  Jong-Hyuk Kim ,  Myang-Sik Han ,  Byung-Jun Hwang

发明人： Kun-Ho Kwak ,  Sung-Jin Kim ,  Soon-Moon Jung ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Hoon Lim ,  Jong-Hyuk Kim ,  Myang-Sik Han ,  Byung-Jun Hwang

IPC分类号： H01L21/00

CPC分类号： H01L27/1108 ,  H01L27/0688 ,  H01L27/11 ,  H01L29/78603

摘要： Methods of fabricating semiconductor devices are provided. An interlayer insulating layer is provided on a single crystalline semiconductor substrate. A single crystalline semiconductor plug is provided that extends through the interlayer insulating layer and a molding layer pattern is provided on the semiconductor substrate and the single crystalline semiconductor plug. The molding layer pattern defines an opening therein that at least partially exposes a portion of the single crystalline semiconductor plug. A single crystalline semiconductor epitaxial pattern is provided on the exposed portion of single crystalline semiconductor plug using a selective epitaxial growth technique that uses the exposed portion of the single crystalline semiconductor plug as a seed layer. A single crystalline semiconductor region is provided in the opening. The single crystalline semiconductor region includes at least a portion of the single crystalline semiconductor epitaxial pattern.

摘要翻译： 提供制造半导体器件的方法。 层间绝缘层设置在单晶半导体衬底上。 提供延伸穿过层间绝缘层的单晶半导体插头，并且在半导体衬底和单晶半导体插头上设置成型层图案。 模制层图案限定其中的开口，其至少部分地暴露单晶半导体插塞的一部分。 使用选择性外延生长技术在单晶半导体插塞的暴露部分上提供单晶半导体外延图案，其使用单晶半导体插塞的暴露部分作为籽晶层。 在开口中设置单晶半导体区域。 单晶半导体区域包括单晶半导体外延图案的至少一部分。

公开(公告)号：US20050184292A1

公开(公告)日：2005-08-25

申请号：US11065750

申请日：2005-02-24

申请人： Kun-Ho Kwak ,  Jae-Hoon Jang ,  Soon-Moon Jung ,  Won-Seok Cho ,  Hoon Lim ,  Sung-Jin Kim ,  Byung-Jun Hwang ,  Jong-Hyuk Kim

发明人： Kun-Ho Kwak ,  Jae-Hoon Jang ,  Soon-Moon Jung ,  Won-Seok Cho ,  Hoon Lim ,  Sung-Jin Kim ,  Byung-Jun Hwang ,  Jong-Hyuk Kim

IPC分类号： H01L21/8244 ,  H01L27/108 ,  H01L27/11

CPC分类号： H01L27/1108 ,  H01L27/11

摘要： Methods of fabricating a semiconductor integrated circuit having thin film transistors using an SEG technique are provided. The methods include forming an inter-layer insulating layer on a single-crystalline semiconductor substrate. A single-crystalline semiconductor plug extends through the inter-layer insulating layer, and a single-crystalline epitaxial semiconductor pattern is in contact with the single-crystalline semiconductor plug on the inter-layer insulating layer. The single-crystalline epitaxial semiconductor pattern is at least partially planarized to form a semiconductor body layer on the inter-layer insulating layer, and the semiconductor body layer is patterned to form a semiconductor body. As a result, the semiconductor body includes at least a portion of the single-crystalline epitaxial semiconductor pattern. Thus, the semiconductor body has an excellent single-crystalline structure. Semiconductor integrated circuits fabricated using the methods are also provided.

摘要翻译： 提供了使用SEG技术制造具有薄膜晶体管的半导体集成电路的方法。 所述方法包括在单晶半导体衬底上形成层间绝缘层。 单晶半导体插件延伸穿过层间绝缘层，并且单晶外延半导体图案与层间绝缘层上的单晶半导体插头接触。 单晶外延半导体图案至少部分地平坦化以在层间绝缘层上形成半导体本体层，并且对半导体本体层进行图案化以形成半导体本体。 结果，半导体本体包括单晶外延半导体图案的至少一部分。 因此，半导体本体具有优异的单晶结构。 还提供了使用这些方法制造的半导体集成电路。

公开(公告)号：US07276404B2

公开(公告)日：2007-10-02

申请号：US11589618

申请日：2006-10-30

申请人： Sung-Jin Kim ,  Soon-Moon Jung ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Kun-Ho Kwak ,  Jong-Hyuk Kim ,  Jae-Joo Shim

发明人： Sung-Jin Kim ,  Soon-Moon Jung ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Kun-Ho Kwak ,  Jong-Hyuk Kim ,  Jae-Joo Shim

IPC分类号： H01L21/00 ,  H01L21/84

CPC分类号： G11C11/412 ,  H01L27/11 ,  H01L27/1108 ,  Y10S257/903

摘要： SRAM cells having landing pads in contact with upper and lower cell gate patterns, and methods of forming the same are provided. The SRAM cells and the methods remove the influence resulting from structural characteristics of the SRAM cells having vertically stacked upper and lower gate patterns, for stably connecting the patterns on the overall surface of the semiconductor substrate. An isolation layer isolating at least one lower active region is formed in a semiconductor substrate of the cell array region. The lower active region has two lower cell gate patterns. A body pattern is disposed in parallel with the semiconductor substrate. The body pattern is formed to confine an upper active region, which has upper cell gate patterns on the lower cell gate patterns. A landing pad is disposed between the lower cell gate patterns. A node pattern is formed to simultaneously contact the upper cell gate pattern and the lower cell gate pattern.