公开(公告)号：US10411119B2

公开(公告)日：2019-09-10

申请号：US15093145

申请日：2016-04-07

申请人： Jae-Hwan Lee ,  Sangsu Kim ,  Sanghyuk Hong ,  Seung Mo Ha

发明人： Jae-Hwan Lee ,  Sangsu Kim ,  Sanghyuk Hong ,  Seung Mo Ha

IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L21/311 ,  H01L29/40 ,  H01L29/08

摘要： A method of fabricating a semiconductor device includes forming an active pattern protruding from a substrate, forming a liner layer on the active pattern, forming a sacrificial gate pattern on the liner layer and crossing the active pattern, forming source/drain regions on the active pattern and at both sides of the sacrificial gate pattern, forming an interlayer insulating layer to cover the source/drain regions, forming capping insulating patterns on the interlayer insulating layer to expose the sacrificial gate pattern, and removing the sacrificial gate pattern and the liner layer by an etching process using the capping insulating patterns as an etch mask to form a gap region exposing the active pattern. The active pattern includes a material having a lattice constant greater than a lattice constant of the substrate, and the capping insulating patterns include a material having an etch selectivity with respect to the liner layer.

公开(公告)号：US20160329414A1

公开(公告)日：2016-11-10

申请号：US15093145

申请日：2016-04-07

申请人： Jae-Hwan LEE ,  Sangsu Kim ,  Sanghyuk Hong ,  Seung Mo Ha

发明人： Jae-Hwan LEE ,  Sangsu Kim ,  Sanghyuk Hong ,  Seung Mo Ha

IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L21/311 ,  H01L29/40

CPC分类号： H01L29/66795 ,  H01L21/823821 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/7851

摘要： A method of fabricating a semiconductor device includes forming an active pattern protruding from a substrate, forming a liner layer on the active pattern, forming a sacrificial gate pattern on the liner layer and crossing the active pattern, forming source/drain regions on the active pattern and at both sides of the sacrificial gate pattern, forming an interlayer insulating layer to cover the source/drain regions, forming capping insulating patterns on the interlayer insulating layer to expose the sacrificial gate pattern, and removing the sacrificial gate pattern and the liner layer by an etching process using the capping insulating patterns as an etch mask to form a gap region exposing the active pattern. The active pattern includes a material having a lattice constant greater than a lattice constant of the substrate, and the capping insulating patterns include a material having an etch selectivity with respect to the liner layer.

摘要翻译： 制造半导体器件的方法包括形成从衬底突出的有源图案，在有源图案上形成衬垫层，在衬垫层上形成牺牲栅极图案并与有源图案交叉，在活性图案上形成源极/漏极区域 在牺牲栅极图案的两侧形成层间绝缘层以覆盖源极/漏极区域，在层间绝缘层上形成覆盖绝缘图案以暴露牺牲栅极图案，以及通过以下步骤去除牺牲栅极图案和衬底层： 使用封盖绝缘图案作为蚀刻掩模的蚀刻工艺来形成暴露活性图案的间隙区域。 活性图案包括晶格常数大于衬底的晶格常数的材料，并且封盖绝缘图案包括相对于衬垫层具有蚀刻选择性的材料。