利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

7 条记录 (耗时 0.017 秒)

    SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME
    4.
    发明申请
    SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME 审中-公开
    半导体器件及其制造方法

    公开(公告)号：US20160307927A1

    公开(公告)日：2016-10-20

    申请号：US14993212

    申请日：2016-01-12

    申请人： Jung-Han Lee ,  Jae-Hwan Lee ,  Sang-Su Kim ,  Hwan-Wook Choi ,  Tae-Jong Lee ,  Seung-Mo Ha

    发明人： Jung-Han Lee ,  Jae-Hwan Lee ,  Sang-Su Kim ,  Hwan-Wook Choi ,  Tae-Jong Lee ,  Seung-Mo Ha

    IPC分类号： H01L27/12 ,  H01L29/06 ,  H01L27/088

    CPC分类号： H01L29/0657 ,  H01L21/823431 ,  H01L21/823468 ,  H01L27/0886

    摘要： A semiconductor device includes a plurality of active fins defined by an isolation layer on a substrate, a gate structure on the active fins and the isolation layer, and a gate spacer structure covering a sidewall of the gate structure. A sidewall of the gate structure includes first, second, and third regions having first, second, and third slopes, respectively. The second slope increases from a bottom toward a top of the second region. The second slope has a value at the bottom of the second region less than the first slope. The third slope is greater than the second slope.

    摘要翻译： 半导体器件包括由衬底上的隔离层限定的多个有源散热片，活性散热片上的栅极结构和隔离层，以及覆盖栅极结构的侧壁的栅极间隔结构。 栅极结构的侧壁分别包括具有第一，第二和第三斜率的第一，第二和第三区域。 第二斜坡从底部向第二区域的顶部增加。 第二斜坡在第二区域的底部具有小于第一斜坡的值。 第三斜率大于第二斜率。

    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
    5.
    发明申请
    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开
    制造半导体器件的方法

    公开(公告)号：US20160307803A1

    公开(公告)日：2016-10-20

    申请号：US15083248

    申请日：2016-03-28

    申请人： Seung-Jin MUN ,  Dong-Hoon KHANG ,  Woo-Ram KIM ,  Cheol KIM ,  Dong-Seok LEE ,  Yong-Joon CHOI ,  Seung-Mo HA ,  Do-Hyoung KIM

    发明人： Seung-Jin MUN ,  Dong-Hoon KHANG ,  Woo-Ram KIM ,  Cheol KIM ,  Dong-Seok LEE ,  Yong-Joon CHOI ,  Seung-Mo HA ,  Do-Hyoung KIM

    IPC分类号： H01L21/8234 ,  H01L21/308

    CPC分类号： H01L21/823431 ,  H01L21/3086 ,  H01L23/544 ,  H01L2223/54426 ,  H01L2223/54453

    摘要： A method of manufacturing a semiconductor device may include forming a sacrificial layer on a substrate including a first region and a second region, forming a first pattern on the sacrificial layer of the second region, forming a second pattern on the sacrificial layer of the first region, forming first upper spacers on opposite sidewalls of the second pattern, removing the second pattern, etching the first sacrificial layer of the first region using the first upper spacers as an etch mask to form a third pattern, etching the first sacrificial layer of the second region using the first pattern as an etch mask to form a fourth pattern, forming first lower spacers at either side of the third pattern, forming second spacers on opposite sidewalls of the fourth pattern, removing the third pattern and the fourth pattern, and etching the substrate using the first lower spacers and the second spacers as etch masks.

    摘要翻译： 制造半导体器件的方法可以包括在包括第一区域和第二区域的衬底上形成牺牲层，在第二区域的牺牲层上形成第一图案，在第一区域的牺牲层上形成第二图案 在所述第二图案的相对侧壁上形成第一上隔片，去除所述第二图案，使用所述第一上隔片作为蚀刻掩模蚀刻所述第一区域的所述第一牺牲层以形成第三图案，蚀刻所述第二图案的所述第一牺牲层 区域，使用第一图案作为蚀刻掩模以形成第四图案，在第三图案的任一侧形成第一下隔片，在第四图案的相对侧壁上形成第二间隔物，去除第三图案和第四图案，并蚀刻 使用第一下隔板和第二间隔件作为蚀刻掩模。

    METHOD OF FABRICATING SEMICONDUCTOR DEVICE
    6.
    发明申请
    METHOD OF FABRICATING SEMICONDUCTOR DEVICE 审中-公开
    制造半导体器件的方法

    公开(公告)号：US20160329414A1

    公开(公告)日：2016-11-10

    申请号：US15093145

    申请日：2016-04-07

    申请人： Jae-Hwan LEE ,  Sangsu Kim ,  Sanghyuk Hong ,  Seung Mo Ha

    发明人： Jae-Hwan LEE ,  Sangsu Kim ,  Sanghyuk Hong ,  Seung Mo Ha

    IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L21/311 ,  H01L29/40

    CPC分类号： H01L29/66795 ,  H01L21/823821 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/7851

    摘要： A method of fabricating a semiconductor device includes forming an active pattern protruding from a substrate, forming a liner layer on the active pattern, forming a sacrificial gate pattern on the liner layer and crossing the active pattern, forming source/drain regions on the active pattern and at both sides of the sacrificial gate pattern, forming an interlayer insulating layer to cover the source/drain regions, forming capping insulating patterns on the interlayer insulating layer to expose the sacrificial gate pattern, and removing the sacrificial gate pattern and the liner layer by an etching process using the capping insulating patterns as an etch mask to form a gap region exposing the active pattern. The active pattern includes a material having a lattice constant greater than a lattice constant of the substrate, and the capping insulating patterns include a material having an etch selectivity with respect to the liner layer.

    摘要翻译： 制造半导体器件的方法包括形成从衬底突出的有源图案，在有源图案上形成衬垫层，在衬垫层上形成牺牲栅极图案并与有源图案交叉，在活性图案上形成源极/漏极区域 在牺牲栅极图案的两侧形成层间绝缘层以覆盖源极/漏极区域，在层间绝缘层上形成覆盖绝缘图案以暴露牺牲栅极图案，以及通过以下步骤去除牺牲栅极图案和衬底层： 使用封盖绝缘图案作为蚀刻掩模的蚀刻工艺来形成暴露活性图案的间隙区域。 活性图案包括晶格常数大于衬底的晶格常数的材料，并且封盖绝缘图案包括相对于衬垫层具有蚀刻选择性的材料。

    Method of fabricating semiconductor device
    7.
    发明授权
    Method of fabricating semiconductor device 有权

    公开(公告)号：US10411119B2

    公开(公告)日：2019-09-10

    申请号：US15093145

    申请日：2016-04-07

    申请人： Jae-Hwan Lee ,  Sangsu Kim ,  Sanghyuk Hong ,  Seung Mo Ha

    发明人： Jae-Hwan Lee ,  Sangsu Kim ,  Sanghyuk Hong ,  Seung Mo Ha

    IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L21/311 ,  H01L29/40 ,  H01L29/08

    摘要： A method of fabricating a semiconductor device includes forming an active pattern protruding from a substrate, forming a liner layer on the active pattern, forming a sacrificial gate pattern on the liner layer and crossing the active pattern, forming source/drain regions on the active pattern and at both sides of the sacrificial gate pattern, forming an interlayer insulating layer to cover the source/drain regions, forming capping insulating patterns on the interlayer insulating layer to expose the sacrificial gate pattern, and removing the sacrificial gate pattern and the liner layer by an etching process using the capping insulating patterns as an etch mask to form a gap region exposing the active pattern. The active pattern includes a material having a lattice constant greater than a lattice constant of the substrate, and the capping insulating patterns include a material having an etch selectivity with respect to the liner layer.