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    NON-VOLATILE MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME
    2.
    发明申请
    NON-VOLATILE MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME 审中-公开
    非易失性存储器件及其制造方法

    公开(公告)号：US20130105877A1

    公开(公告)日：2013-05-02

    申请号：US13614028

    申请日：2012-09-13

    申请人： Kyoung-Hoon KIM ,  Hong-Soo KIM ,  Hoo-Sung CHO

    发明人： Kyoung-Hoon KIM ,  Hong-Soo KIM ,  Hoo-Sung CHO

    IPC分类号： H01L27/105 ,  H01L21/8239

    CPC分类号： H01L29/66825 ,  H01L21/76232 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/66833

    摘要： A non-volatile memory device includes a substrate including an active region and a field region, selection transistors and cell transistors on the active region, bit line contacts on the bridge portions, and shared bit lines electrically connected to the bit line contacts. The active region includes string portions and bridge portions. The string portions extends in a first direction and is arranged in a second direction substantially perpendicular to the first direction, and the bridge portions connects at least two adjacent string portions. Each bridge portion has a length in the first direction equal to or longer than about twice a width of each bit line contact in the first direction.

    摘要翻译： 非易失性存储器件包括：衬底，其包括有源区域和场区域，有源区域上的选择晶体管和单元晶体管，桥接部分上的位线接触，以及电连接到位线触点的共享位线。 有源区域包括串部分和桥接部分。 弦线部分沿第一方向延伸并且布置在基本上垂直于第一方向的第二方向上，并且桥接部分连接至少两个相邻的线部分。 每个桥接部分具有在第一方向上的长度等于或大于每个位线接触件在第一方向上的宽度的大约两倍。

    FULL CMOS SRAM
    3.
    发明申请
    FULL CMOS SRAM 失效
    全CMOS SRAM

    公开(公告)号：US20100195375A1

    公开(公告)日：2010-08-05

    申请号：US12686545

    申请日：2010-01-13

    申请人： Han-byung PARK ,  Hoon Ijm ,  Hoo-Sung Cho

    发明人： Han-byung PARK ,  Hoon Ijm ,  Hoo-Sung Cho

    IPC分类号： G11C11/00 ,  H01L27/11

    CPC分类号： H01L27/1104 ,  G11C11/412 ,  H01L27/0688 ,  H01L27/11

    摘要： A full complementary metal-oxide semiconductor (CMOS) static random access memory (SRAM) may have a reduced cell size by arranging a word line of a pair of transistors arranged on the uppermost layer of the SRAM. First and second transistors may be arranged on first and second active regions. Third and fourth transistors may be arranged on first and second semiconductor layers formed over the first and second active regions. Fifth and sixth transistors may be arranged on the third and fourth semiconductor layers over the first and second semiconductor layers. A word line may be arranged in a straight line between the first and second gates of the first and second transistors and between the third and fourth gates of the third and fourth transistors.

    摘要翻译： 通过布置在SRAM的最上层的一对晶体管的字线，完全互补的金属氧化物半导体（CMOS）静态随机存取存储器（SRAM）可以具有减小的单元尺寸。 第一和第二晶体管可以布置在第一和第二有源区上。 第三和第四晶体管可以布置在形成在第一和第二有源区上的第一和第二半导体层上。 第五和第六晶体管可以布置在第一和第二半导体层上的第三和第四半导体层上。 字线可以布置在第一和第二晶体管的第一和第二栅极之间以及第三和第四晶体管的第三和第四栅极之间的直线上。

    Semiconductor device with three-dimensional array structure
    4.
    发明授权
    Semiconductor device with three-dimensional array structure 有权
    具有三维阵列结构的半导体器件

    公开(公告)号：US07646664B2

    公开(公告)日：2010-01-12

    申请号：US11869140

    申请日：2007-10-09

    申请人： Hoo-Sung Cho ,  Soon-Moon Jung ,  Young-Seop Rah ,  Jae-Hoon Jang ,  Jae-Hun Jeong ,  Jun-Beom Park

    发明人： Hoo-Sung Cho ,  Soon-Moon Jung ,  Young-Seop Rah ,  Jae-Hoon Jang ,  Jae-Hun Jeong ,  Jun-Beom Park

    IPC分类号： G11C8/00

    CPC分类号： G11C8/10 ,  G11C8/08 ,  G11C8/14 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1116 ,  H01L27/112 ,  H01L27/11286 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11568

    摘要： A semiconductor memory device including a memory cell array, a first row decoder adjacent the memory cell array, and a second row decoder adjacent the memory cell array. A memory cell array may include first and second memory cell blocks on respective first and second semiconductor layers. The first memory cell block may include a first word line coupled to a first row of memory cells on the first semiconductor layer, the second memory cell block may include a second word line coupled to a second row of memory cells on the second semiconductor layer, and the first word line may be between the first and second semiconductor layers. The first row decoder may be configured to control the first word line, and the second row decoder may be configured to control the second word line. A first wiring may electrically connect the first row decoder and the first word line, and a second wiring may electrically connect the second row decoder and the second word line.

    摘要翻译： 一种半导体存储器件，包括存储单元阵列，与存储单元阵列相邻的第一行解码器以及与存储单元阵列相邻的第二行解码器。 存储单元阵列可以包括在相应的第一和第二半导体层上的第一和第二存储单元块。 第一存储单元块可以包括耦合到第一半导体层上的第一行存储单元的第一字线，第二存储单元块可以包括耦合到第二半导体层上的第二行存储单元的第二字线， 并且第一字线可以在第一和第二半导体层之间。 第一行解码器可以被配置为控制第一字线，并且第二行解码器可以被配置为控制第二字线。 第一布线可以电连接第一行解码器和第一字线，并且第二布线可电连接第二行解码器和第二字线。

    Semiconductor memory device
    5.
    发明申请
    Semiconductor memory device 审中-公开
    半导体存储器件

    公开(公告)号：US20100001337A1

    公开(公告)日：2010-01-07

    申请号：US12456537

    申请日：2009-06-18

    申请人： Han-Soo Kim ,  Jae-Hoon Jang ,  Hoo-Sung Cho

    发明人： Han-Soo Kim ,  Jae-Hoon Jang ,  Hoo-Sung Cho

    IPC分类号： H01L29/792 ,  H01L29/66

    CPC分类号： H01L27/11551 ,  H01L27/0207 ,  H01L27/0688

    摘要： A semiconductor memory device includes: sequentially stacked first and second semiconductor layers; at least one first memory transistor disposed on the first semiconductor layer; and at least one second memory transistor disposed on the second semiconductor layer, wherein a gate electrode of the first memory transistor has a broader width than that of the second memory transistor.

    摘要翻译： 半导体存储器件包括：顺序堆叠的第一和第二半导体层; 设置在所述第一半导体层上的至少一个第一存储晶体管; 以及设置在所述第二半导体层上的至少一个第二存储晶体管，其中所述第一存储晶体管的栅电极具有比所述第二存储晶体管宽的宽度。

    SEMICONDUCTOR DEVICE WITH RESISTOR AND METHOD OF FABRICATING SAME
    6.
    发明申请
    SEMICONDUCTOR DEVICE WITH RESISTOR AND METHOD OF FABRICATING SAME 审中-公开
    具有电阻器的半导体器件及其制造方法

    公开(公告)号：US20090278189A1

    公开(公告)日：2009-11-12

    申请号：US12434718

    申请日：2009-05-04

    申请人： Hoo-Sung CHO ,  Kyoung-Hoon KIM ,  Nok-Hyun JU

    发明人： Hoo-Sung CHO ,  Kyoung-Hoon KIM ,  Nok-Hyun JU

    IPC分类号： H01L27/06 ,  H01L29/788

    CPC分类号： H01L27/0688 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551

    摘要： A semiconductor device includes a cell array region disposed on a semiconductor substrate and comprising a first cell gate pattern, a cell semiconductor pattern disposed on the first cell gate pattern, and a second cell gate pattern disposed on the cell semiconductor pattern. The semiconductor device also includes a peripheral circuit region disposed on the semiconductor substrate and comprising a peripheral gate pattern, and a resistor disposed in the peripheral circuit region at level above the semiconductor substrate similar to that of the cell semiconductor pattern.

    摘要翻译： 半导体器件包括设置在半导体衬底上并包括第一单元栅极图案，设置在第一单元栅极图案上的单元半导体图案以及设置在单元半导体图案上的第二单元栅极图案的单元阵列区域。 半导体器件还包括设置在半导体衬底上并包括外围栅极图案的外围电路区域和设置在类似于电池半导体图案的半导体衬底上方的外围电路区域中的电阻器。

    SEMICONDUCTOR DEVICE WITH THREE-DIMENSIONAL ARRAY STRUCTURE
    7.
    发明申请
    SEMICONDUCTOR DEVICE WITH THREE-DIMENSIONAL ARRAY STRUCTURE 有权
    具有三维阵列结构的半导体器件

    公开(公告)号：US20080084729A1

    公开(公告)日：2008-04-10

    申请号：US11869140

    申请日：2007-10-09

    申请人： Hoo-Sung Cho ,  Soon-Moon Jung ,  Young-Seop Rah ,  Jae-Hoon Jang ,  Jae-Hun Jeong ,  Jun-Beom Park

    发明人： Hoo-Sung Cho ,  Soon-Moon Jung ,  Young-Seop Rah ,  Jae-Hoon Jang ,  Jae-Hun Jeong ,  Jun-Beom Park

    IPC分类号： G11C5/06

    CPC分类号： G11C8/10 ,  G11C8/08 ,  G11C8/14 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1116 ,  H01L27/112 ,  H01L27/11286 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11568

    摘要： A semiconductor memory device including a memory cell array, a first row decoder adjacent the memory cell array, and a second row decoder adjacent the memory cell array. A memory cell array may include first and second memory cell blocks on respective first and second semiconductor layers. The first memory cell block may include a first word line coupled to a first row of memory cells on the first semiconductor layer, the second memory cell block may include a second word line coupled to a second row of memory cells on the second semiconductor layer, and the first word line may be between the first and second semiconductor layers. The first row decoder may be configured to control the first word line, and the second row decoder may be configured to control the second word line. A first wiring may electrically connect the first row decoder and the first word line, and a second wiring may electrically connect the second row decoder and the second word line.

    摘要翻译： 一种半导体存储器件，包括存储单元阵列，与存储单元阵列相邻的第一行解码器以及与存储单元阵列相邻的第二行解码器。 存储单元阵列可以包括在相应的第一和第二半导体层上的第一和第二存储单元块。 第一存储单元块可以包括耦合到第一半导体层上的第一行存储单元的第一字线，第二存储单元块可以包括耦合到第二半导体层上的第二行存储单元的第二字线， 并且第一字线可以在第一和第二半导体层之间。 第一行解码器可以被配置为控制第一字线，并且第二行解码器可以被配置为控制第二字线。 第一布线可以电连接第一行解码器和第一字线，并且第二布线可电连接第二行解码器和第二字线。

    Semiconductor device having body contact through gate and method of fabricating the same
    10.
    发明申请
    Semiconductor device having body contact through gate and method of fabricating the same 有权

    公开(公告)号：US20060019434A1

    公开(公告)日：2006-01-26

    申请号：US11177447

    申请日：2005-07-07

    申请人： Jae-Hun Jeong ,  Hoon Lim ,  Hoo-Sung Cho

    发明人： Jae-Hun Jeong ,  Hoon Lim ,  Hoo-Sung Cho

    IPC分类号： H01L21/84 ,  H01L21/8238

    CPC分类号： H01L21/76838 ,  H01L21/8221 ,  H01L27/0688

    摘要： According to an embodiment of the invention, a lower transistor is formed on a semiconductor substrate, and an upper thin film transistor is formed on the lower transistor. A body contact plug is formed to penetrate an upper gate electrode of the upper thin film transistor and a body pattern, and to electrically connect with a lower gate electrode of the lower transistor. The body contact plug uses a contact hole to apply an electrical signal to the upper gate electrode of the upper thin film transistor, so additional volume is not necessary. Since the upper gate electrode is electrically connected to the body pattern through the body contact plug, the floating body effect of the upper thin film transistor can be improved. Therefore, a semiconductor device is provided with the high performance required to realize a highly-integrated semiconductor device.